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Low-Power Design and Power-Aware Verification (Hardcover, 1st ed. 2018)
Loot Price: R3,875
Discovery Miles 38 750
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Low-Power Design and Power-Aware Verification (Hardcover, 1st ed. 2018)
Expected to ship within 12 - 17 working days
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Until now, there has been a lack of a complete knowledge base to
fully comprehend Low power (LP) design and power aware (PA)
verification techniques and methodologies and deploy them all
together in a real design verification and implementation project.
This book is a first approach to establishing a comprehensive PA
knowledge base. LP design, PA verification, and Unified Power
Format (UPF) or IEEE-1801 power format standards are no longer
special features. These technologies and methodologies are now part
of industry-standard design, verification, and implementation flows
(DVIF). Almost every chip design today incorporates some kind of
low power technique either through power management on chip, by
dividing the design into different voltage areas and controlling
the voltages, through PA dynamic and PA static verification, or
their combination. The entire LP design and PA verification process
involves thousands of techniques, tools, and methodologies,
employed from the r egister transfer level (RTL) of design
abstraction down to the synthesis or place-and-route levels of
physical design. These techniques, tools, and methodologies are
evolving everyday through the progression of design-verification
complexity and more intelligent ways of handling that complexity by
engineers, researchers, and corporate engineering policy makers.
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