Test Generation of Crosstalk Delay Faults in VLSI Circuits (Hardcover, 1st ed. 2019)

This book describes a variety of test generation algorithms for testing crosstalk delay faults in VLSI circuits. It introduces readers to the various crosstalk effects and describes both deterministic and simulation-based methods for testing crosstalk delay faults. The book begins with a focus on currently available crosstalk delay models, test generation algorithms for delay faults and crosstalk delay faults, before moving on to deterministic algorithms and simulation-based algorithms used to test crosstalk delay faults. Given its depth of coverage, the book will be of interest to design engineers and researchers in the field of VLSI Testing.

General

Imprint:	Springer Verlag, Singapore
Country of origin:	Singapore
Release date:	September 2018
First published:	2019
Authors:	S. Jayanthy • M.C. Bhuvaneswari
Dimensions:	235 x 155mm (L x W)
Format:	Hardcover
Pages:	156
Edition:	1st ed. 2019
ISBN-13:	978-981-13-2492-5
Categories:	Books > Computing & IT > General theory of computing > Systems analysis & design Books > Computing & IT > General theory of computing > Data structures Books > Computing & IT > Computer programming > Algorithms & procedures Books > Professional & Technical > Electronics & communications engineering > Electronics engineering > Circuits & components Books > Computing & IT > Computer hardware & operating systems > Computer architecture & logic design > General
LSN:	981-13-2492-1
Barcode:	9789811324925

Is the information for this product incomplete, wrong or inappropriate? Let us know about it.

Does this product have an incorrect or missing image? Send us a new image.

Is this product missing categories? Add more categories.

Review This Product

No reviews yet - be the first to create one!