Formal Equivalence Checking and Design Debugging covers two major
topics in design verification: logic equivalence checking and
design debugging. The first part of the book reviews the design
problems that require logic equivalence checking and describes the
underlying technologies that are used to solve them. Some novel
approaches to the problems of verifying design revisions after
intensive sequential transformations such as retiming are described
in detail. The second part of the book gives a thorough survey of
previous and recent literature on design error diagnosis and design
error correction. This part also provides an in-depth analysis of
the algorithms used in two logic debugging software programs,
ErrorTracer and AutoFix, developed by the authors. From the
Foreword: With the adoption of the static sign-off approach to
verifying circuit implementations the application-specific
integrated circuit (ASIC) industry will experience the first
radical methodological revolution since the adoption of logic
synthesis. Equivalence checking is one of the two critical elements
of this methodological revolution. This book is timely for either
the designer seeking to better understand the mechanics of
equivalence checking or for the CAD researcher who wishes to
investigate well-motivated research problems such as equivalence
checking of retimed designs or error diagnosis in sequential
circuits.' Kurt Keutzer, University of California, Berkeley
General
| Imprint: |
Springer
|
| Country of origin: |
Netherlands |
| Series: |
Frontiers in Electronic Testing, 12 |
| Release date: |
June 1998 |
| First published: |
June 1998 |
| Authors: |
Shi-Yu Huang
• Kwang-Ting (Tim) Cheng
|
| Dimensions: |
235 x 155 x 15mm (L x W x T) |
| Format: |
Hardcover
|
| Pages: |
229 |
| Edition: |
1998 ed. |
| ISBN-13: |
978-0-7923-8184-6 |
| Categories: |
Books >
Computing & IT >
Computer programming >
General
|
| LSN: |
0-7923-8184-X |
| Barcode: |
9780792381846 |
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