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Designing Reliable and Efficient Networks on Chips (Paperback, Softcover reprint of hardcover 1st ed. 2009) Loot Price: R4,203
Discovery Miles 42 030
Repayment Terms: R394 pm x 12*
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Designing Reliable and Efficient Networks on Chips (Paperback, Softcover reprint of hardcover 1st ed. 2009): Srinivasan Murali

Designing Reliable and Efficient Networks on Chips (Paperback, Softcover reprint of hardcover 1st ed. 2009)

Srinivasan Murali

Series: Lecture Notes in Electrical Engineering, 34

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Loot Price R4,203 Discovery Miles 42 030 | Repayment Terms: R394 pm x 12*

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Developing NoC based interconnect tailored to a particular application domain, satisfying the application performance constraints with minimum power-area overhead is a major challenge. With technology scaling, as the geometries of on-chip devices reach the physical limits of operation, another important design challenge for NoCs will be to provide dynamic (run-time) support against permanent and intermittent faults that can occur in the system. The purpose of Designing Reliable and Efficient Networks on Chips is to provide state-of-the-art methods to solve some of the most important and time-intensive problems encountered during NoC design.

General

Imprint: Springer
Country of origin: Netherlands
Series: Lecture Notes in Electrical Engineering, 34
Release date: October 2010
First published: 2009
Authors: Srinivasan Murali
Dimensions: 235 x 155 x 11mm (L x W x T)
Format: Paperback
Pages: 198
Edition: Softcover reprint of hardcover 1st ed. 2009
ISBN-13: 978-90-481-8200-8
Categories: Books > Professional & Technical > Energy technology & engineering > Electrical engineering > General
Books > Professional & Technical > Electronics & communications engineering > Electronics engineering > Circuits & components
Books > Computing & IT > Computer hardware & operating systems > Computer architecture & logic design > General
LSN: 90-481-8200-X
Barcode: 9789048182008

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