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Books > Computing & IT > Computer hardware & operating systems > Computer architecture & logic design
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Advanced HDL Synthesis and SOC Prototyping - RTL Design Using Verilog (Hardcover, 1st ed. 2019)
Loot Price: R4,818
Discovery Miles 48 180
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Advanced HDL Synthesis and SOC Prototyping - RTL Design Using Verilog (Hardcover, 1st ed. 2019)
Expected to ship within 12 - 17 working days
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This book describes RTL design using Verilog, synthesis and timing
closure for System On Chip (SOC) design blocks. It covers the
complex RTL design scenarios and challenges for SOC designs and
provides practical information on performance improvements in SOC,
as well as Application Specific Integrated Circuit (ASIC) designs.
Prototyping using modern high density Field Programmable Gate
Arrays (FPGAs) is discussed in this book with the practical
examples and case studies. The book discusses SOC design,
performance improvement techniques, testing and system level
verification, while also describing the modern Intel FPGA/XILINX
FPGA architectures and their use in SOC prototyping. Further, the
book covers the Synopsys Design Compiler (DC) and Prime Time (PT)
commands, and how they can be used to optimize complex ASIC/SOC
designs. The contents of this book will be useful to students and
professionals alike.
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