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Books > Computing & IT > Computer hardware & operating systems > Computer architecture & logic design
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ASIC Design and Synthesis - RTL Design Using Verilog (Hardcover, 1st ed. 2021)
Loot Price: R5,300
Discovery Miles 53 000
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ASIC Design and Synthesis - RTL Design Using Verilog (Hardcover, 1st ed. 2021)
Expected to ship within 10 - 15 working days
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This book describes simple to complex ASIC design practical
scenarios using Verilog. It builds a story from the basic
fundamentals of ASIC designs to advanced RTL design concepts using
Verilog. Looking at current trends of miniaturization, the contents
provide practical information on the issues in ASIC design and
synthesis using Synopsys DC and their solution. The book explains
how to write efficient RTL using Verilog and how to improve design
performance. It also covers architecture design strategies,
multiple clock domain designs, low-power design techniques, DFT,
pre-layout STA and the overall ASIC design flow with case studies.
The contents of this book will be useful to practicing hardware
engineers, students, and hobbyists looking to learn about ASIC
design and synthesis.
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