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Many-Core Computing - Hardware and software (Hardcover): Bashir M. Al-Hashimi, Geoff V. Merrett Many-Core Computing - Hardware and software (Hardcover)
Bashir M. Al-Hashimi, Geoff V. Merrett
R4,091 R3,680 Discovery Miles 36 800 Save R411 (10%) Ships in 10 - 15 working days

Computing has moved away from a focus on performance-centric serial computation, instead towards energy-efficient parallel computation. This provides continued performance increases without increasing clock frequencies, and overcomes the thermal and power limitations of the dark-silicon era. As the number of parallel cores increases, we transition into the many-core computing era. There is considerable interest in developing methods, tools, architectures and applications to support many-core computing. The primary aim of this edited book is to provide a timely and coherent account of the recent advances in many-core computing research. Starting with programming models, operating systems and their applications; the authors present runtime management techniques, followed by system modelling, verification and testing methods, and architectures and systems. The book ends with some examples of innovative applications.

System-on-Chip - Next generation electronics (Hardcover, New): Bashir M. Al-Hashimi System-on-Chip - Next generation electronics (Hardcover, New)
Bashir M. Al-Hashimi
R4,444 R3,977 Discovery Miles 39 770 Save R467 (11%) Ships in 10 - 15 working days

System-on-Chip (SoC) is believed to represent the next major market for microelectronics, and there is a considerable interest world-wide in developing effective methods and tools to support the SoC paradigm. The field of SoC is broad and expanding and at present the technical and technological literature about the overall state-of-the-art in SoC is dispersed across a wide spectrum of books, journals, and conference proceedings. This edited book is an attempt to provide a comprehensive and accessible source of state-of-the-art information on existing and emerging SoC key research areas. In particular, the book covers the general principles and ideas of designing, validating and testing complex embedded computing systems and their underlying tradeoffs. Twenty-five international research groups have contributed to the book. Each contribution has an up-to-date survey highlighting the key achievements and future trends. To facilitate the understanding of the various topics covered in the book, each chapter has some background covering the basic principles, and extensive list of references. To enhance the book readability, the chapters are grouped into eight parts, each part examining a particular theme of SoC, including system design, embedded software, power management, reconfigurable computing, network-on-chip, verification and test. The book will be of interest to graduate students, designers and managers working in Electronic and Computer engineering.

System-Level Design Techniques for Energy-Efficient Embedded Systems (Hardcover, 2004 ed.): Marcus T. Schmitz, Bashir M.... System-Level Design Techniques for Energy-Efficient Embedded Systems (Hardcover, 2004 ed.)
Marcus T. Schmitz, Bashir M. Al-Hashimi, Petru Eles
R2,996 Discovery Miles 29 960 Ships in 10 - 15 working days

System-Level Design Techniques for Energy-Efficient Embedded Systems addresses the development and validation of co-synthesis techniques that allow an effective design of embedded systems with low energy dissipation. The book provides an overview of a system-level co-design flow, illustrating through examples how system performance is influenced at various steps of the flow including allocation, mapping, and scheduling. The book places special emphasis upon system-level co-synthesis techniques for architectures that contain voltage scalable processors, which can dynamically trade off between computational performance and power consumption. Throughout the book, the introduced co-synthesis techniques, which target both single-mode systems and emerging multi-mode applications, are applied to numerous benchmarks and real-life examples including a realistic smart phone.

Power-Constrained Testing of VLSI Circuits - A Guide to the IEEE 1149.4 Test Standard (Hardcover, 2003 ed.): Nicola Nicolici,... Power-Constrained Testing of VLSI Circuits - A Guide to the IEEE 1149.4 Test Standard (Hardcover, 2003 ed.)
Nicola Nicolici, Bashir M. Al-Hashimi
R2,979 Discovery Miles 29 790 Ships in 10 - 15 working days

This text focuses on techniques for minimizing power dissipation during test application at logic and register-transfer levels of abstraction of the VLSI design flow. It surveys existing techniques and presents several test automation techniques for reducing power in scan-based sequential circuits and BIST data paths.

Power-Constrained Testing of VLSI Circuits - A Guide to the IEEE 1149.4 Test Standard (Paperback, Softcover reprint of the... Power-Constrained Testing of VLSI Circuits - A Guide to the IEEE 1149.4 Test Standard (Paperback, Softcover reprint of the original 1st ed. 2003)
Nicola Nicolici, Bashir M. Al-Hashimi
R2,843 Discovery Miles 28 430 Ships in 10 - 15 working days

Minimization of power dissipation in very large scale integrated (VLSI) circuits is important to improve reliability and reduce packaging costs. While many techniques have investigated power minimization during the functional (normal) mode of operation, it is important to examine the power dissipation during the test circuit activity is substantially higher during test than during functional operation. For example, during the execution of built-in self-test (BIST) in-field sessions, excessive power dissipation can decrease the reliability of the circuit under test due to higher temperature and current density.

Power-Constrained Testing of VLSI Circuits focuses on techniques for minimizing power dissipation during test application at logic and register-transfer levels of abstraction of the VLSI design flow. The first part of this book surveys the existing techniques for power constrained testing of VLSI circuits. In the second part, several test automation techniques for reducing power in scan-based sequential circuits and BIST data paths are presented.

System-Level Design Techniques for Energy-Efficient Embedded Systems (Paperback, 1st ed. Softcover of orig. ed. 2004): Marcus... System-Level Design Techniques for Energy-Efficient Embedded Systems (Paperback, 1st ed. Softcover of orig. ed. 2004)
Marcus T. Schmitz, Bashir M. Al-Hashimi, Petru Eles
R2,852 Discovery Miles 28 520 Ships in 10 - 15 working days

System-Level Design Techniques for Energy-Efficient Embedded Systems addresses the development and validation of co-synthesis techniques that allow an effective design of embedded systems with low energy dissipation. The book provides an overview of a system-level co-design flow, illustrating through examples how system performance is influenced at various steps of the flow including allocation, mapping, and scheduling. The book places special emphasis upon system-level co-synthesis techniques for architectures that contain voltage scalable processors, which can dynamically trade off between computational performance and power consumption. Throughout the book, the introduced co-synthesis techniques, which target both single-mode systems and emerging multi-mode applications, are applied to numerous benchmarks and real-life examples including a realistic smart phone.

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