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System-on-Chip Test Architectures, Volume . - Nanometer Design for Testability (Hardcover): Laung-terng Wang, Charles E.... System-on-Chip Test Architectures, Volume . - Nanometer Design for Testability (Hardcover)
Laung-terng Wang, Charles E. Stroud, Nur A. Touba
R1,768 Discovery Miles 17 680 Ships in 12 - 17 working days

Modern electronics testing has a legacy of more than 40 years. The introduction of new technologies, especially nanometer technologies with 90nm or smaller geometry, has allowed the semiconductor industry to keep pace with the increased performance-capacity demands from consumers. As a result, semiconductor test costs have been growing steadily and typically amount to 40% of today's overall product cost.
This book is a comprehensive guide to new VLSI Testing and Design-for-Testability techniques that will allow students, researchers, DFT practitioners, and VLSI designers to master quickly System-on-Chip Test architectures, for test debug and diagnosis of digital, memory, and analog/mixed-signal designs.
KEY FEATURES
* Emphasizes VLSI Test principles and Design for Testability architectures, with numerous illustrations/examples.
* Most up-to-date coverage available, including Fault Tolerance, Low-Power Testing, Defect and Error Tolerance, Network-on-Chip (NOC) Testing, Software-Based Self-Testing, FPGA Testing, MEMS Testing, and System-In-Package (SIP) Testing, which are not yet available in any testing book.
* Covers the entire spectrum of VLSI testing and DFT architectures, from digital and analog, to memory circuits, and fault diagnosis and self-repair from digital to memory circuits.
* Discusses future nanotechnology test trends and challenges facing the nanometer design era; promising nanotechnology test techniques, including Quantum-Dots, Cellular Automata, Carbon-Nanotubes, and Hybrid Semiconductor/Nanowire/Molecular Computing.
* Practical problems at the end of each chapter for students.

A Designer's Guide to Built-In Self-Test (Hardcover, 2002 ed.): Charles E. Stroud A Designer's Guide to Built-In Self-Test (Hardcover, 2002 ed.)
Charles E. Stroud
R5,903 Discovery Miles 59 030 Ships in 10 - 15 working days

A recent technological advance is the art of designing circuits to test themselves, referred to as a Built-In Self-Test. This book is written from a designer's perspective and describes the major BIST approaches that have been proposed and implemented, along with their advantages and limitations.

A Designer's Guide to Built-In Self-Test (Paperback, Softcover reprint of the original 1st ed. 2002): Charles E. Stroud A Designer's Guide to Built-In Self-Test (Paperback, Softcover reprint of the original 1st ed. 2002)
Charles E. Stroud
R5,717 Discovery Miles 57 170 Ships in 10 - 15 working days

A recent technological advance is the art of designing circuits to test themselves, referred to as a Built-In Self-Test. This book is written from a designer's perspective and describes the major BIST approaches that have been proposed and implemented, along with their advantages and limitations.

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