Computational intelligence techniques are becoming more and more important for automated problem solving nowadays. Due to the growing complexity of industrial applications and the increasingly tight time-to-market requirements, the time available for thorough problem analysis and development of tailored solution methods is decreasing. There is no doubt that this trend will continue in the foreseeable future. Hence, it is not surprising that robust and general automated problem solving methods with satisfactory performance are needed.

This book focuses on modeling, simulation and analysis of analog circuit aging. First, all important nanometer CMOS physical effects resulting in circuit unreliability are reviewed. Then, transistor aging compact models for circuit simulation are discussed and several methods for efficient circuit reliability simulation are explained and compared. Ultimately, the impact of transistor aging on analog circuits is studied. Aging-resilient and aging-immune circuits are identified and the impact of technology scaling is discussed. The models and simulation techniques described in the book are intended as an aid for device engineers, circuit designers and the EDA community to understand and to mitigate the impact of aging effects on nanometer CMOS ICs.

This book investigates the possible circuit solutions to overcome the temperature and supply voltage-sensitivity of fully-integrated time references for ultra-low-power communication in wireless sensor networks. The authors provide an elaborate theoretical introduction and literature study to enable full understanding of the design challenges and shortcomings of current oscillator implementations. Furthermore, a closer look to the short-term as well as the long-term frequency stability of integrated oscillators is taken. Next, a design strategy is developed and applied to 5 different oscillator topologies and 1 sensor interface. All 6 implementations are subject to an elaborate study of frequency stability, phase noise and power consumption. In the final chapter all blocks are compared to the state of the art.

Computational intelligence techniques are becoming more and more important for automated problem solving nowadays. Due to the growing complexity of industrial applications and the increasingly tight time-to-market requirements, the time available for thorough problem analysis and development of tailored solution methods is decreasing. There is no doubt that this trend will continue in the foreseeable future. Hence, it is not surprising that robust and general automated problem solving methods with satisfactory performance are needed.

This unique book provides an overview of the current state of the art and very recent research results that have been achieved as part of the Low-Power Initiative of the European Union, in the field of analogue, RF and mixed-signal design methodologies and CAD tools.

This text addresses the design methodologies and CAD tools available for the systematic design and design automation of analogue integrated circuits. Two complementary approaches discussed increase analogue design productivity, demonstrated throughout using design times of the different design experiments undertaken.

This book focuses on modeling, simulation and analysis of analog circuit aging. First, all important nanometer CMOS physical effects resulting in circuit unreliability are reviewed. Then, transistor aging compact models for circuit simulation are discussed and several methods for efficient circuit reliability simulation are explained and compared. Ultimately, the impact of transistor aging on analog circuits is studied. Aging-resilient and aging-immune circuits are identified and the impact of technology scaling is discussed.

The models and simulation techniques described in the book are intended as an aid for device engineers, circuit designers and the EDA community to understand and to mitigate the impact of aging effects on nanometer CMOS ICs.

This book brings together important contributions and state-of-the-art research results in the rapidly advancing area of symbolic analysis of analog circuits. It is also of interest to those working in analog CAD. The book is an excellent reference, providing insights into some of the most important issues in the symbolic analysis of analog circuits.

It is a great honor to provide a few words of introduction for Dr. Georges Gielen's and Prof. Willy Sansen's book "Symbolic analysis for automated design of analog integrated circuits." The symbolic analysis method presented in this book represents a significant step forward in the area of analog circuit design. As demonstrated in this book, symbolic analysis opens up new possibilities for the development of computer-aided design (CAD) tools that can analyze an analog circuit topology and automatically size the components for a given set of specifications. Symbolic analysis even has the potential to improve the training of young analog circuit designers and to guide more experienced designers through second-order phenomena such as distortion. This book can also serve as an excellent reference for researchers in the analog circuit design area and creators of CAD tools, as it provides a comprehensive overview and comparison of various approaches for analog circuit design automation and an extensive bibliography. The world is essentially analog in nature, hence most electronic systems involve both analog and digital circuitry. As the number of transistors that can be integrated on a single integrated circuit (IC) substrate steadily increases over time, an ever increasing number of systems will be implemented with one, or a few, very complex ICs because of their lower production costs.

This book introduces a design methodology that can help to bridge the productivity gap. Two different types of designs, depending on the design challenge, have been identified. To validate the presented methodologies, the authors have selected and designed accordingly three different industrial-strength applications.

This book describes new tools for front end analog designers, starting with global variation-aware sizing, and extending to novel variation-aware topology design. The tools aid design through automation, but more importantly, they also aid designer insight through automation. We now describe four design tasks, each more general than the previous, and how this book contributes design aids and insight aids to each. The ?rst designer task targeted is global robust sizing. This task is supported by a design tool that does automated, globally reliable, variation-aware s- ing (SANGRIA), and an insight-aiding tool that extracts designer-interpretable whitebox models that relate sizings to circuit performance (CAFFEINE). SANGRIA searches on several levels of problem dif?culty simultaneously, from lower cheap-to-evaluate "exploration" layers to higher full-evaluation "exploitation" layers (structural homotopy). SANGRIAmakes maximal use of circuit simulations by performing scalable data mining on simulation results to choose new candidate designs. CAFFEINE accomplishes its task by tre- ing function induction as a tree-search problem. It constrains its tree search space via a canonical-functional-form grammar, and searches the space with grammatically constrained genetic programming. The second designer task is topology selection/topology design. Topology selection tools must consider a broad variety of topologies such that an app- priate topology is selected, must easily adapt to new semiconductor process nodes, and readily incorporate new topologies. Topology design tools must allow designers to creatively explore new topology ideas as rapidly as possible.

nalog circuits are fascinating artifacts. They manipulate signals whose informa- Ationcontentisrichcomparedtodigitalsignalsthatcarryminimalamountofinf- mation;theyaredelicateinthatanyperturbationduetoparasiticelements,todelays,to interactionswithotherelementsandwiththeenvironmentmaycauseasigni?cantloss ofinformation. Thedif?cultyindealingwiththeseartifactsistoprotectthemfromall possibleattacks, evenminorones, fromthephysicalworld. Theironyisthattheyare oftenusedtofunnelinformationfromandtothephysicalworldtoandfromtheabstr- tionofthedigitalworldandforthisfunction, theyareirreplaceable. Nowonderthen that analog designers form a club of extraordinary gentlemen where art (or magic?) ratherthanscienceisthesharedtrade. Theyaredif?culttotrainsinceexperienceand intuitionarethetraitsthat characterize them. Andthey have dif?cultiesinexplaining what is the process they use to reach satisfactory results. Tools used for design (s- ulation) are mainly replacing the test benches of an experimental lab. However, the growing complexity of the integrated systems being designed today together with the increasing fragility of analog components brought about by shrinking geometries and reducedpowerconsumptionisposingseverechallengestotraditionalanalogdesigners to produce satisfactory results in a short time. At the same time, the need for expe- enced analog designers has increased constantly since almost all designs, because of integration,docontainanalogcomponents. Thissituationhascreatedastronginterest in developing design methodologies and supporting tools that are based on rigorous, mathematically literate, approaches. Doing so will make it possible to leverage the expertiseofseasonedanalogdesignersandtotrainnewgenerationsfasterandbetter. Inthepast, severalattemptshavebeenmadeinacademia andindustrytocreatethese methodologies and to extend the set of tools available. They have had questionable acceptance in the analog design community. However, recently, a ?urry of start-ups andincreasedinvestmentbyEDAcompaniesinnoveltoolssignalasigni?cantchange inmarketattentiontotheanalogdomain. Ipersonallybelievethattosubstantially- prove quality and design time, tools are simply insuf?cient. A design methodology based on a hierarchy of abstraction layers, successive re?nement between two ad- cent layers, and extensive veri?cation at every layer is necessary. To do so, we need to build theories and models that have strong mathematical foundations. The analog design technology community is as strong as it has ever been.

Analog integrated circuits are very important as interfaces between the digital parts of integrated electronic systems and the outside world. A large portion of the effort involved in designing these circuits is spent in the layout phase. Whereas the physical design of digital circuits is automated to a large extent, the layout of analog circuits is still a manual, time-consuming and error-prone task. This is mainly due to the continuous nature of analog signals, which causes analog circuit performance to be very sensitive to layout parasitics. The parasitic elements associated with interconnect wires cause loading and coupling effects that degrade the frequency behaviour and the noise performance of analog circuits. Device mismatch and thermal effects put a fundamental limit on the achievable accuracy of circuits. For successful automation of analog layout, advanced place and route tools that can handle these critical parasitics are required. In the past, automatic analog layout tools tried to optimize the layout without quantifying the performance degradation introduced by layout parasitics. Therefore, it was not guaranteed that the resulting layout met the specifications and one or more layout iterations could be needed. In Analog Layout Generation for Performance and Manufacturability, the authors propose a performance driven layout strategy to overcome this problem. In this methodology, the layout tools are driven by performance constraints, such that the final layout, with parasitic effects, still satisfies the specifications of the circuit. The performance degradation associated with an intermediate layout solution is evaluated at runtime using predetermined sensitivities. In contrast with other performance driven layout methodologies, the tools proposed in this book operate directly on the performance constraints, without an intermediate parasitic constraint generation step. This approach makes a complete and sensible trade-off between the different layout alternatives possible at runtime and therefore eliminates the possible feedback route between constraint derivation, placement and layout extraction. Besides its influence on the performance, layout also has a profound impact on the yield and testability of an analog circuit. In Analog Layout Generation for Performance and Manufacturability, the authors outline a new criterion to quantify the detectability of a fault and combine this with a yield model to evaluate the testability of an integrated circuit layout. They then integrate this technique with their performance driven routing algorithm to produce layouts that have optimal manufacturability while still meeting their performance specifications. Analog Layout Generation for Performance and Manufacturability will be of interest to analog engineers, researchers and students.

This book is the first in a series of three dedicated to advanced topics in Mixed-Signal IC design methodologies. It is one of the results achieved by the Mixed-Signal Design Cluster, an initiative launched in 1998 as part of the TARDIS project, funded by the European Commission within the ESPRIT-IV Framework. This initiative aims to promote the development of new design and test methodologies for Mixed-Signal ICs, and to accelerate their adoption by industrial users. As Microelectronics evolves, Mixed-Signal techniques are gaining a significant importance due to the wide spread of applications where an analog front-end is needed to drive a complex digital-processing subsystem. In this sense, Analog and Mixed-Signal circuits are recognized as a bottleneck for the market acceptance of Systems-On-Chip, because of the inherent difficulties involved in the design and test of these circuits. Specially, problems arising from the use of a common substrate for analog and digital components are a main limiting factor. The Mixed-Signal Cluster has been formed by a group of 11 Research and Development projects, plus a specific action to promote the dissemination of design methodologies, techniques, and supporting tools developed within the Cluster projects. The whole action, ending in July 2002, has been assigned an overall budget of more than 8 million EURO.

Various approaches for finding optimal values for the parameters of analog cells have made their entrance in commercial applications. However, a larger impact on the performance is expected if tools are developed which operate on a higher abstraction level and consider multiple architectural choices to realize a particular functionality. This book examines the opportunities, conditions, problems, solutions and systematic methodologies for this new generation of analog CAD tools.

nalog circuits are fascinating artifacts. They manipulate signals whose informa- Ationcontentisrichcomparedtodigitalsignalsthatcarryminimalamountofinf- mation;theyaredelicateinthatanyperturbationduetoparasiticelements, todelays, to interactionswithotherelementsandwiththeenvironmentmaycauseasigni?cantloss ofinformation. Thedif?cultyindealingwiththeseartifactsistoprotectthemfromall possibleattacks, evenminorones, fromthephysicalworld. Theironyisthattheyare oftenusedtofunnelinformationfromandtothephysicalworldtoandfromtheabstr- tionofthedigitalworldandforthisfunction, theyareirreplaceable. Nowonderthen that analog designers form a club of extraordinary gentlemen where art (or magic?) ratherthanscienceisthesharedtrade. Theyaredif?culttotrainsinceexperienceand intuitionarethetraitsthat characterize them. Andthey have dif?cultiesinexplaining what is the process they use to reach satisfactory results. Tools used for design (s- ulation) are mainly replacing the test benches of an experimental lab. However, the growing complexity of the integrated systems being designed today together with the increasing fragility of analog components brought about by shrinking geometries and reducedpowerconsumptionisposingseverechallengestotraditionalanalogdesigners to produce satisfactory results in a short time. At the same time, the need for expe- enced analog designers has increased constantly since almost all designs, because of integration, docontainanalogcomponents. Thissituationhascreatedastronginterest in developing design methodologies and supporting tools that are based on rigorous, mathematically literate, approaches. Doing so will make it possible to leverage the expertiseofseasonedanalogdesignersandtotrainnewgenerationsfasterandbetter. Inthepast, severalattemptshavebeenmadeinacademia andindustrytocreatethese methodologies and to extend the set of tools available. They have had questionable acceptance in the analog design community. However, recently, a ?urry of start-ups andincreasedinvestmentbyEDAcompaniesinnoveltoolssignalasigni?cantchange inmarketattentiontotheanalogdomain. Ipersonallybelievethattosubstantially- prove quality and design time, tools are simply insuf?cient. A design methodology based on a hierarchy of abstraction layers, successive re?nement between two ad- cent layers, and extensive veri?cation at every layer is necessary. To do so, we need to build theories and models that have strong mathematical foundations. The analog design technology community is as strong as it has ever be

Systematic Design of Analog IP Blocks introduces a design methodology that can help to bridge the productivity gap. Two different types of designs, depending on the design challenge, have been identified: commodity IP and star IP. Each category requires a different approach to boost design productivity. Commodity IP blocks are well suited to be automated in an analog synthesis environment and provided as soft IP. The design knowledge is usually common knowledge, and reuse is high accounting for the setup time needed for the analog library. Star IP still changes as technology evolves and the design cost can only be reduced by following a systematic design approach supported by point tools to relieve the designer from error-prone, repetitive tasks, allowing him/her to focus on new ideas to push the limits of the design.

Driven by applications such as telecommunications, computing and consumer/multimedia and facilitated by the progress in CMOS ULSI technology, the microelectronics IC market is characterized by an ever-increasing level of integration complexity. Today complete systems, that previously occupied one or more boards, are integrated on a few chips or even on one single multi-million transistor chip - a so called System-on-Chip (SoC). Although most functions in such integrated systems are implemented with digital or digital signal processing circuitry, the analog circuits needed at the interface between the electronic system and the continuous-valued outside world are also being integrated on the same die for reasons of cost and performance.

Unfortunately, the integration of both analog & RF circuits and digital circuits on the same die not only offers many benefits, but also creates some technical difficulties. Since the analog circuits exploit the low-level physics of the fabrication process, they remain difficult and costly to design, but they are also vulnerable to any kind of noise or crosstalk signals. The higher levels of integration (moving towards 100 million transistors per chip clocked at ever higher frequencies) make the mixed-signal signal integrity problem increasingly challenging. One of the most important problems is the parasitic supply and substrate noise coupling, caused by the fast switching of the digital circuitry that then propagates to the sensitive analog circuitry via the common substrate. It is therefore important to be able to predict the impact of digital switching noise on the analog circuit performance at the design stage of the integrated system, beforethe chip is taped out for fabrication, and to understand how this problem can be reduced.

The purpose of Substrate Noise Coupling in Mixed-Signal ASICs is to provide an overview of very recent research results in the field of substrate noise analysis and reduction techniques. Much of the reported work has been established as part of the Mixed-Signal Initiative of the European Union. It is a representative sampling of the current state of the art in this area. All the different aspects of the substrate noise coupling problem are covered. Some chapters describe techniques to model and reduce the digital switching noise injected in the substrate. Other chapters describe methods to analyse the propagation of the noise from the source (the digital circuitry) to the reception point (the embedded analog circuitry) through the substrate considered as a resistive/capacitive mesh. Finally, the remaining chapters describe techniques to model and especially to reduce the impact of substrate noise on the analog side. This is illustrated with several practical design examples and measurement results.

This text addresses the design methodologies and CAD tools available for the systematic design and design automation of analogue integrated circuits. Two complementary approaches discussed increase analogue design productivity, demonstrated throughout using design times of the different design experiments undertaken.

This unique book provides an overview of the current state of the art and very recent research results that have been achieved as part of the Low-Power Initiative of the European Union, in the field of analogue, RF and mixed-signal design methodologies and CAD tools.

Analog integrated circuits are very important as interfaces between the digital parts of integrated electronic systems and the outside world. A large portion of the effort involved in designing these circuits is spent in the layout phase. Whereas the physical design of digital circuits is automated to a large extent, the layout of analog circuits is still a manual, time-consuming and error-prone task. This is mainly due to the continuous nature of analog signals, which causes analog circuit performance to be very sensitive to layout parasitics. The parasitic elements associated with interconnect wires cause loading and coupling effects that degrade the frequency behaviour and the noise performance of analog circuits. Device mismatch and thermal effects put a fundamental limit on the achievable accuracy of circuits. For successful automation of analog layout, advanced place and route tools that can handle these critical parasitics are required. In the past, automatic analog layout tools tried to optimize the layout without quantifying the performance degradation introduced by layout parasitics. Therefore, it was not guaranteed that the resulting layout met the specifications and one or more layout iterations could be needed. In Analog Layout Generation for Performance and Manufacturability, the authors propose a performance driven layout strategy to overcome this problem. In this methodology, the layout tools are driven by performance constraints, such that the final layout, with parasitic effects, still satisfies the specifications of the circuit. The performance degradation associated with an intermediate layout solution is evaluated at runtime using predetermined sensitivities. In contrast with other performance driven layout methodologies, the tools proposed in this book operate directly on the performance constraints, without an intermediate parasitic constraint generation step. This approach makes a complete and sensible trade-off between the different layout alternatives possible at runtime and therefore eliminates the possible feedback route between constraint derivation, placement and layout extraction. Besides its influence on the performance, layout also has a profound impact on the yield and testability of an analog circuit. In Analog Layout Generation for Performance and Manufacturability, the authors outline a new criterion to quantify the detectability of a fault and combine this with a yield model to evaluate the testability of an integrated circuit layout. They then integrate this technique with their performance driven routing algorithm to produce layouts that have optimal manufacturability while still meeting their performance specifications. Analog Layout Generation for Performance and Manufacturability will be of interest to analog engineers, researchers and students.

This book brings together important contributions and state-of-the-art research results in the rapidly advancing area of symbolic analysis of analog circuits. It is also of interest to those working in analog CAD. The book is an excellent reference, providing insights into some of the most important issues in the symbolic analysis of analog circuits.

It is a great honor to provide a few words of introduction for Dr. Georges Gielen's and Prof. Willy Sansen's book "Symbolic analysis for automated design of analog integrated circuits." The symbolic analysis method presented in this book represents a significant step forward in the area of analog circuit design. As demonstrated in this book, symbolic analysis opens up new possibilities for the development of computer-aided design (CAD) tools that can analyze an analog circuit topology and automatically size the components for a given set of specifications. Symbolic analysis even has the potential to improve the training of young analog circuit designers and to guide more experienced designers through second-order phenomena such as distortion. This book can also serve as an excellent reference for researchers in the analog circuit design area and creators of CAD tools, as it provides a comprehensive overview and comparison of various approaches for analog circuit design automation and an extensive bibliography. The world is essentially analog in nature, hence most electronic systems involve both analog and digital circuitry. As the number of transistors that can be integrated on a single integrated circuit (IC) substrate steadily increases over time, an ever increasing number of systems will be implemented with one, or a few, very complex ICs because of their lower production costs.

Various approaches for finding optimal values for the parameters of analog cells have made their entrance in commercial applications. However, a larger impact on the performance is expected if tools are developed which operate on a higher abstraction level and consider multiple architectural choices to realize a particular functionality. This book examines the opportunities, conditions, problems, solutions and systematic methodologies for this new generation of analog CAD tools.

This book describes new tools for front end analog designers, starting with global variation-aware sizing, and extending to novel variation-aware topology design. The tools aid design through automation, but more importantly, they also aid designer insight through automation. We now describe four design tasks, each more general than the previous, and how this book contributes design aids and insight aids to each. The ?rst designer task targeted is global robust sizing. This task is supported by a design tool that does automated, globally reliable, variation-aware s- ing (SANGRIA), and an insight-aiding tool that extracts designer-interpretable whitebox models that relate sizings to circuit performance (CAFFEINE). SANGRIA searches on several levels of problem dif?culty simultaneously, from lower cheap-to-evaluate "exploration" layers to higher full-evaluation "exploitation" layers (structural homotopy). SANGRIAmakes maximal use of circuit simulations by performing scalable data mining on simulation results to choose new candidate designs. CAFFEINE accomplishes its task by tre- ing function induction as a tree-search problem. It constrains its tree search space via a canonical-functional-form grammar, and searches the space with grammatically constrained genetic programming. The second designer task is topology selection/topology design. Topology selection tools must consider a broad variety of topologies such that an app- priate topology is selected, must easily adapt to new semiconductor process nodes, and readily incorporate new topologies. Topology design tools must allow designers to creatively explore new topology ideas as rapidly as possible.