On high-performance embedded computing, we are witnessing the trend to integrate multiple cores in Multi-Processor Systems-on-Chip (MPSoCs). Networks- on-chip (NoCs) have been proposed to be a scalable, predictable and flexible paradigm to design complex NoC-based Many-core MPSoCs. However, since the number of cores increases exponentially, new challenges such as the design of suitable NoCs, and how to exploit parallelism on a chip arise. In this book, we showour EDA tool (xENoC - NoCMaker) that allows design, simulation and fast-prototype of NoC-based systems, as well as the trade-offs on the design of Network Interfaces (NI) to provide interoperability between cores of different protocols (AMBA/OCP-IP) with Quality-of-Service (QoS) support at a reasonable power and area costs. In the second part, the book tries to shed light on system-level software, runtime QoS support and middleware APIs, and a MPI-like parallel programming model (ocMPI), which offers SW programmers a way to express message-passing parallelism on NoC-based MPSoCs. This book should be especially useful for researchers on the field of parallel embedded computing on many- core on-chip systems.

Nowadays Embedded Systems require high performance specific computations, usually with real-time and Quality of Service constraints, which should run at a low energy level to extend battery life and avoid heating. Very Long Instruction Word (VLIW) processors are a good solution providing enough computational performance at low power with the required programmability to meet short time-to-market restrictions. For those architectures with a high number of computational resources running in parallel the access to data is becoming the main bottleneck that limits the available parallelism. The purpose of this work is to prove that optimizing address generation is an effective of accessing data while decreasing execution time and energy consumption. First, this work evaluates the effectiveness of VLIW processors and presents the architectural exploration framework used for the experiments. It also presents a systematic classification of address generators, a review of literature according to the classification of the different optimizations on the address generation process and a step-wise methodology that gradually reduces energy.

One advantage of using a virtual platform over real hardware for embedded software development and testing is the ability of some simulators to take checkpoints of their state. If the entire system model is detailed enough, it might take several minutes (or hours) to simulate booting the O.S. If a snapshot of the simulation is saved just after it has finished booting, each time it is necessary to run the embedded software, designers can simply restore the snapshot and go. Restarting a checkpoint typically takes a few seconds. In this book we present our work on adding a description level language as SystemC to two Virtual Platforms. This work was done for a commercial Virtual Platform, and later translated to a open-sourced Platform. This book also presents a set of modifications to SystemC language to support checkpointing. These modifications will make it possible to take the state of a SystemC running simulation and save it to disk. Later, the same simulation can be restored to the same point it was before, without any change to the simulated modules. These changes would help SystemC to be suitable for use by Virtual Platforms as a description language.

This book presents the mapping of the same multimedia application (MPEG-4) into different platforms used in the embedded domain. The design flow is described in Matlab and translated to C++ language. Afterward, the code is refined and optimised for the execution on multiple platforms: an embedded platform formed by a high performance DSP and an embedded processor, an Application Specific Instruction Processor(ASIP), a specific hardware implemented in an FPGA for accelerating the data-flow part of the system with a soft-core for the control part, and an Application Specific Integrated Circuit(ASIC). One of the main contributions is to show a fair comparison of the same multimedia application implemented in diverse platforms. Another, it is to illustrate a methodology that can be generalised to different Data Dominant applications. New methodology allows to obtain near optimal implementation from concept to silicon and it can be extended to any hybrid HW/SW multimedia platform. We evaluate the different transformations to arrive at an optimal implementation; that allow achieving better results than using more precise effort in mapping the design in the physical level.