Focussing on micro- and nanoelectronics design and technology, this book provides thorough analysis and demonstration, starting from semiconductor devices to VLSI fabrication, designing (analog and digital), on-chip interconnect modeling culminating with emerging non-silicon/ nano devices. It gives detailed description of both theoretical as well as industry standard HSPICE, Verilog, Cadence simulation based real-time modeling approach with focus on fabrication of bulk and nano-devices. Each chapter of this proposed title starts with a brief introduction of the presented topic and ends with a summary indicating the futuristic aspect including practice questions. Aimed at researchers and senior undergraduate/graduate students in electrical and electronics engineering, microelectronics, nanoelectronics and nanotechnology, this book: Provides broad and comprehensive coverage from Microelectronics to Nanoelectronics including design in analog and digital electronics. Includes HDL, and VLSI design going into the nanoelectronics arena. Discusses devices, circuit analysis, design methodology, and real-time simulation based on industry standard HSPICE tool. Explores emerging devices such as FinFETs, Tunnel FETs (TFETs) and CNTFETs including their circuit co-designing. Covers real time illustration using industry standard Verilog, Cadence and Synopsys simulations.

Recent advances in semiconductor technology offer vertical interconnect access (via) that extend through silicon, popularly known as through silicon via (TSV). This book provides a comprehensive review of the theory behind TSVs while covering most recent advancements in materials, models and designs. Furthermore, depending on the geometry and physical configurations, different electrical equivalent models for Cu, carbon nanotube (CNT) and graphene nanoribbon (GNR) based TSVs are presented. Based on the electrical equivalent models the performance comparison among the Cu, CNT and GNR based TSVs are also discussed.

The brief primarily focuses on the performance analysis of CNT based interconnects in current research scenario. Different CNT structures are modeled on the basis of transmission line theory. Performance comparison for different CNT structures illustrates that CNTs are more promising than Cu or other materials used in global VLSI interconnects. The brief is organized into five chapters which mainly discuss: (1) an overview of current research scenario and basics of interconnects; (2) unique crystal structures and the basics of physical properties of CNTs, and the production, purification and applications of CNTs; (3) a brief technical review, the geometry and equivalent RLC parameters for different single and bundled CNT structures; (4) a comparative analysis of crosstalk and delay for different single and bundled CNT structures; and (5) various unique mixed CNT bundle structures and their equivalent electrical models.

Focussing on micro- and nanoelectronics design and technology, this book provides thorough analysis and demonstration, starting from semiconductor devices to VLSI fabrication, designing (analog and digital), on-chip interconnect modeling culminating with emerging non-silicon/ nano devices. It gives detailed description of both theoretical as well as industry standard HSPICE, Verilog, Cadence simulation based real-time modeling approach with focus on fabrication of bulk and nano-devices. Each chapter of this proposed title starts with a brief introduction of the presented topic and ends with a summary indicating the futuristic aspect including practice questions. Aimed at researchers and senior undergraduate/graduate students in electrical and electronics engineering, microelectronics, nanoelectronics and nanotechnology, this book: Provides broad and comprehensive coverage from Microelectronics to Nanoelectronics including design in analog and digital electronics. Includes HDL, and VLSI design going into the nanoelectronics arena. Discusses devices, circuit analysis, design methodology, and real-time simulation based on industry standard HSPICE tool. Explores emerging devices such as FinFETs, Tunnel FETs (TFETs) and CNTFETs including their circuit co-designing. Covers real time illustration using industry standard Verilog, Cadence and Synopsys simulations.

Recent advances in semiconductor technology offer vertical interconnect access (via) that extend through silicon, popularly known as through silicon via (TSV). This book provides a comprehensive review of the theory behind TSVs while covering most recent advancements in materials, models and designs. Furthermore, depending on the geometry and physical configurations, different electrical equivalent models for Cu, carbon nanotube (CNT) and graphene nanoribbon (GNR) based TSVs are presented. Based on the electrical equivalent models the performance comparison among the Cu, CNT and GNR based TSVs are also discussed.