This book contains papers presented at the fifth and sixth Teraflop Workshop. It presents the state-of-the-art in high performance computing and simulation on modern supercomputer architectures. It covers trends in hardware and software development in general and specifically the future of vector-based systems and heterogeneous architectures. It covers computational fluid dynamics, fluid-structure interaction, physics, chemistry, astrophysics, and climate research.

This book covers the results obtained in the Tera op Workbench project during a four years period from 2004 to 2008. The Tera op Workbench project is a colla- ration betweenthe High PerformanceComputingCenter Stuttgart (HLRS) and NEC Deutschland GmbH (NEC-HPCE) to support users to achieve their research goals using high performance computing. The Tera op Workbench supports users of the HLRS systems to enable and - cilitate leading edge scienti c research. This is achieved by optimizing their codes and improving the process work ow which results from the integration of diff- ent modules into a "hybrid vector system". The assessment and demonstration of industrial relevance is another goal of the cooperation. The Tera op Workbench project consists of numerous individual codes, grouped together by application area and developed and maintained by researchers or c- mercial organizations. Within the project, several of the codes have shown the ab- ity to reach beyond the TFlop/s threshold of sustained performance. This created the possibility for new science and a deeper understanding of the underlying physics. The papers in this book demonstrate the value of the project for different scienti c areas.

Learn to assess electromigration reliability and design more resilient chips in this comprehensive and practical resource. Beginning with fundamental physics and building to advanced methodologies, this book enables the reader to develop highly reliable on-chip wiring stacks and power grids. Through a detailed review on the role of microstructure, interfaces and processing on electromigration reliability, as well as characterisation, testing and analysis, the book follows the development of on-chip interconnects from microscale to nanoscale. Practical modeling methodologies for statistical analysis, from simple 1D approximation to complex 3D description, can be used for step-by-step development of reliable on-chip wiring stacks and industrial-grade power/ground grids. This is an ideal resource for materials scientists and reliability and chip design engineers.

This book covers the results of the Tera op Workbench, other projects related to High Performance Computing, and the usage of HPC installations at HLRS. The Tera op Workbench project is a collaboration between the High Performance C- puting Center Stuttgart (HLRS) and NEC Deutschland GmbH (NEC-HPCE) to s- port users in achieving their research goals using High Performance Computing. The rst stage of the Tera op Workbench project (2004-2008) concentrated on user's applications and their optimization for the former ag ship of HLRS, a - node NEC SX-8 installation. During this stage, numerous individual codes, dev- oped and maintained by researchers or commercial organizations, have been a- lyzed and optimized. Within the project, several of the codes have shown the ability to outreach the TFlop/s threshold of sustained performance. This created the pos- bility for new science and a deeper understanding of the underlying physics. The second stage of the Tera op Workbench project (2008-2012) focuses on c- rent and future trends of hardware and software developments. We observe a strong tendency to heterogeneous environments on the hardware level, while at the same time, applications become increasingly heterogeneous by including multi-physics or multi-scale effects. The goal of the current studies of the Tera op Workbench is to gain insight in the developments of both components. The overall target is to help scientists to run their application in the most ef cient and most convenient way on the hardware best suited for their purposes.

This book covers the results of the 11th and 12th Tera?op Workshop and continued a series initiated by NEC and the HLRS in 2004. As part of the Tera?op Workbench, it has become a meeting platform for scientists, application developers, international experts and hardware designers to discuss the current state and future directions of supercomputing with the aim of achieving the highest sustained application perf- mance. The Tera?op Workbench Project is a collaboration between the High Perf- mance Computing Center Stuttgart (HLRS) and NEC Deutschland GmbH (NEC HPCE) to support users to achieve their research goals using High Performance Computing. The ?rst stage of the Tera?op Workbench project (2004-2008) c- centrated on user's applications and their optimization for the 72-node NEC SX-8 installation at HLRS. During this stage, numerous individual codes, developed and maintained by researchers or commercial organizations, have been analyzed and - timized. Several of the codes have shown the ability to outreach the TFlop/s thre- old of sustained performance. This created the possibility for new science and a deeper understanding of the underlying physics.

This book contains papers presented at the fifth and sixth Teraflop Workshop. It presents the state-of-the-art in high performance computing and simulation on modern supercomputer architectures. It covers trends in hardware and software development in general and specifically the future of vector-based systems and heterogeneous architectures. It covers computational fluid dynamics, fluid-structure interaction, physics, chemistry, astrophysics, and climate research.

This book covers the results obtained in the Tera op Workbench project during a four years period from 2004 to 2008. The Tera op Workbench project is a colla- ration betweenthe High PerformanceComputingCenter Stuttgart (HLRS) and NEC Deutschland GmbH (NEC-HPCE) to support users to achieve their research goals using high performance computing. The Tera op Workbench supports users of the HLRS systems to enable and - cilitate leading edge scienti c research. This is achieved by optimizing their codes and improving the process work ow which results from the integration of diff- ent modules into a "hybrid vector system." The assessment and demonstration of industrial relevance is another goal of the cooperation. The Tera op Workbench project consists of numerous individual codes, grouped together by application area and developed and maintained by researchers or c- mercial organizations. Within the project, several of the codes have shown the ab- ity to reach beyond the TFlop/s threshold of sustained performance. This created the possibility for new science and a deeper understanding of the underlying physics. The papers in this book demonstrate the value of the project for different scienti c areas.

Enabled by the development and introduction of new materials, the semiconductor industry continues to follow Moore's law into 32nm and 22nm technologies. Advanced interconnect structures require the use of porous dielectrics with further reduced k-values and even weaker mechanical properties, as well as much thinner metallization liners. In addition, the increasing resistivity of Cu at decreasing dimensions must be addressed in order to maintain the performance of continuously shrinking devices. To deal with these issues, and to maintain the reliability of the interconnects, innovations in materials, processes and architectures are needed. This book brings together researchers from around the world to exchange the latest advances in materials, processes, integration and reliability in advanced interconnects and packaging, and to discuss interconnects for emerging technologies. Papers from a joint session with Symposium F, Packaging, Chip-Package Interactions and Solder Materials Challenges, are also included and focus on 3D chip stacking and molecular electronics.

Enabled by the development and introduction of new materials, the semiconductor industry continues to follow Moore's law into 32nm and 22nm technologies. Advanced interconnect structures require the use of porous dielectrics with further reduced k-values and even weaker mechanical properties, as well as much thinner metallization liners. In addition, the increasing resistivity of Cu at decreasing dimensions must be addressed in order to maintain the performance of continuously shrinking devices. To deal with these issues, and to maintain the reliability of the interconnects, innovations in materials, processes and architectures are needed. This book brings together researchers from around the world to exchange the latest advances in materials, processes, integration and reliability in advanced interconnects and packaging, and to discuss interconnects for emerging technologies. Papers from a joint session with Symposium F, Packaging, Chip-Package Interactions and Solder Materials Challenges, are also included and focus on 3D chip stacking and molecular electronics.