With the growth of high-speed telecommunications and wireless technology, it is becoming increasingly important for engineers to understand radio frequency (RF) applications and their sensitivity to electrostatic discharge (ESD) phenomena. This enables the development of ESD design methods for RF technology, leading to increased protection against electrical overstress (EOS) and ESD.

ESD: RF Technology and Circuits: Presents methods for co-synthesizisng ESD networks for RF applications to achieve improved performance and ESD protection of semiconductor chips; discusses RF ESD design methods of capacitance load transformation, matching network co-synthesis, capacitance shunts, inductive shunts, impedance isolation, load cancellation methods, distributed loads, emitter degeneration, buffering and ballasting; examines ESD protection and design of active and passive elements in RF complementary metal-oxide-semiconductor (CMOS), RF laterally-diffused metal oxide semiconductor (LDMOS), RF BiCMOS Silicon Germanium (SiGe), RF BiCMOS Silicon Germanium Carbon (SiGeC), and Gallim Arsenide technology; gives information on RF ESD testing methodologies, RF degradation effects, and failure mechanisms for devices, circuits and systems; highlights RF ESD mixed-signal design integration of digital, analog and RF circuitry; sets out examples of RF ESD design computer aided design methodologies; covers state-of-the-art RF ESD input circuits, as well as voltage-triggered to RC-triggered ESD power clamps networks in RF technologies, as well as off-chip protection concepts.

Following the authors series of books on ESD, this book will be a thorough overview of ESD in RF technology for RF semiconductorchip and ESD engineers. Device and circuit engineers working in the RF domain, and quality, reliability and failure analysis engineers will also find it a valuable reference in the rapidly growing are of RF ESD design. In addition, it will appeal to graduate students in RF microwave technology and RF circuit design.

This volume is the first in a series of three books addressing Electrostatic Discharge (ESD) physics, devices, circuits and design across the full range of integrated circuit technologies. "ESD Physics and Devices" provides a concise treatment of the ESD phenomenon and the physics of devices operating under ESD conditions. Voldman presents an accessible introduction to the field for engineers and researchers requiring a solid grounding in this important area. The book contains advanced CMOS, Silicon On Insulator, Silicon Germanium, and Silicon Germanium Carbon. In addition, it also addresses ESD in advanced CMOS with discussions on shallow trench isolation (STI), Copper and Low K materials.This book provides a clear understanding of ESD device physics and the fundamentals of ESD phenomena. It analyses the behaviour of semiconductor devices under ESD conditions. It addresses the growing awareness of the problems resulting from ESD phenomena in advanced integrated circuits. It covers ESD testing, failure criteria and scaling theory for CMOS, SOI (silicon on insulator), BiCMOS and BiCMOS SiGe (Silicon Germanium) technologies for the first time. It discusses the design and development implications of ESD in semiconductor technologies. It is an invaluable reference for EMC non-specialist engineers and researchers working in the fields of IC and transistor design. It is also suitable for researchers and advanced students in the fields of device/circuit modelling and semiconductor reliability.

ESD: Circuits and Devices 2nd Edition provides a clear picture of layout and design of digital, analog, radio frequency (RF) and power applications for protection from electrostatic discharge (ESD), electrical overstress (EOS), and latchup phenomena from a generalist perspective and design synthesis practices providing optimum solutions in advanced technologies. New features in the 2nd edition: * Expanded treatment of ESD and analog design of passive devices of resistors, capacitors, inductors, and active devices of diodes, bipolar junction transistors, MOSFETs, and FINFETs. * Increased focus on ESD power clamps for power rails for CMOS, Bipolar, and BiCMOS. * Co-synthesizing of semiconductor chip architecture and floor planning with ESD design practices for analog, and mixed signal applications * Illustrates the influence of analog design practices on ESD design circuitry, from integration, synthesis and layout, to symmetry, matching, inter-digitation, and common centroid techniques. * Increased emphasis on system-level testing conforming to IEC 61000-4-2 and IEC 61000-4-5. * Improved coverage of low-capacitance ESD, scaling of devices and oxide scaling challenges. ESD: Circuits and Devices 2nd Edition is an essential reference to ESD, circuit & semiconductor engineers and quality, reliability &analysis engineers. It is also useful for graduate and undergraduate students in electrical engineering, semiconductor sciences, microelectronics and IC design.

Interest in latchup is being renewed with the evolution of complimentary metal-oxide semiconductor (CMOS) technology, metal-oxide-semiconductor field-effect transistor (MOSFET) scaling, and high-level system-on-chip (SOC) integration.

Clear methodologies that grant protection from latchup, with insight into the physics, technology and circuit issues involved, are in increasing demand.

This book describes CMOS and BiCMOS semiconductor technology and their sensitivity to present day latchup phenomena, from basic over-voltage and over-current conditions, single event latchup (SEL) and cable discharge events (CDE), to latchup domino phenomena. It contains chapters focusing on bipolar physics, latchup theory, latchup and guard ring characterization structures, characterization testing, product level test systems, product level testing and experimental results. Discussions on state-of-the-art semiconductor processes, design layout, and circuit level and system level latchup solutions are also included, as well as:

latchup semiconductor process solutions for both CMOS to BiCMOS, such as shallow trench, deep trench, retrograde wells, connecting implants, sub-collectors, heavily-doped buried layers, and buried grids - from single- to triple-well CMOS; practical latchup design methods, automated and bench-level latchup testing methods and techniques, latchup theory of logarithm resistance space, generalized alpha (a) space, beta (b) space, new latchup design methods- connecting the theoretical to the practical analysis, and; examples of latchup computer aided design (CAD) methodologies, from design rule checking (DRC) and logical-to-physical design, to new latchup CAD methodologiesthat address latchup for internal and external latchup on a local as well as global design level.

"Latchup" acts as a companion text to the author's series of books on ESD (electrostatic discharge) protection, serving as an invaluable reference for the professional semiconductor chip and system-level ESD engineer. Semiconductor device, process and circuit designers, and quality, reliability and failure analysis engineers will find it informative on the issues that confront modern CMOS technology. Practitioners in the automotive and aerospace industries will also find it useful. In addition, its academic treatment will appeal to both senior and graduate students with interests in semiconductor process, device physics, computer aided design and design integration.

A practical and comprehensive reference that explores Electrostatic Discharge (ESD) in semiconductor components and electronic systems The ESD Handbook offers a comprehensive reference that explores topics relevant to ESD design in semiconductor components and explores ESD in various systems. Electrostatic discharge is a common problem in the semiconductor environment and this reference fills a gap in the literature by discussing ESD protection. Written by a noted expert on the topic, the text offers a topic-by-topic reference that includes illustrative figures, discussions, and drawings. The handbook covers a wide-range of topics including ESD in manufacturing (garments, wrist straps, and shoes); ESD Testing; ESD device physics; ESD semiconductor process effects; ESD failure mechanisms; ESD circuits in different technologies (CMOS, Bipolar, etc.); ESD circuit types (Pin, Power, Pin-to-Pin, etc.); and much more. In addition, the text includes a glossary, index, tables, illustrations, and a variety of case studies. Contains a well-organized reference that provides a quick review on a range of ESD topics Fills the gap in the current literature by providing information from purely scientific and physical aspects to practical applications Offers information in clear and accessible terms Written by the accomplished author of the popular ESD book series Written for technicians, operators, engineers, circuit designers, and failure analysis engineers, The ESD Handbook contains an accessible reference to ESD design and ESD systems.

Invention and patents continues to be an important issue in technology and our global economy. Invention and Patenting provides a clear picture of how to be a prolific inventor, to understand patents, and the patent process. It provides an illuminating insight into the writing of invention disclosures to patents from the submission process to final drafts. The book shows how to communicate effectively with patent lawyers and patent examiners, teaching the language of "legalese." This book is unique in covering both the early invention process to final patent drafting to provide high quality patents in technologies. Key features include: How to become an inventor, how to invent, to what is invention; How to write an invention disclosure to writing a patent; Examples of utility, design, and plant patents; How to prepare the background section, brief listing of figures, detailed description of the invention, claims, abstract to artwork; Using patent search engines; Writing independent and dependent claims; Analyzing office actions of the US and European patent offices; How to write an office action response and amending claims; and, Examples of Office Action responses, preliminary amendments, to notice of allowance response; Invention and Patenting is the first book by an engineer and inventor from a technologist's point of view. It is an essential reference for engineers and inventors. It is also useful for graduate and undergraduate students in technology and the sciences.

Electrostatic discharge (ESD) continues to impact semiconductor components and systems as technologies scale from micro- to nano-electronics.

This book studies electrical overstress, ESD, and latchup from a whole-chip ESD design synthesis approach. It provides a clear insight into the integration of ESD protection networks from a generalist perspective, followed by examples in specific technologies, circuits, and chips. Uniquely both the semiconductor chip integration issues and floorplanning of ESD networks are covered from a 'top-down' design approach.

Look inside for extensive coverage on: integration of cores, power bussing, and signal pins in DRAM, SRAM, CMOS image processing chips, microprocessors, analog products, RF components and how the integration influences ESD design and integrationarchitecturing of mixed voltage, mixed signal, to RF design for ESD analysisfloorplanning for peripheral and core I/O designs, and the implications on ESD and latchupguard ring integration for both a 'bottom-up' and 'top-down' methodology addressing I/O guard rings, ESD guard rings, I/O to I/O, and I/O to coreclassification of ESD power clamps and ESD signal pin circuitry, and how to make the correct choice for a given semiconductor chipexamples of ESD design for the state-of-the-art technologies discussed, including CMOS, BiCMOS, silicon on insulator (SOI), bipolar technology, high voltage CMOS (HVCMOS), RF CMOS, and smart powerpractical methods for the understanding of ESD circuit power distribution, ground rule development, internal bus distribution, current path analysis, quality metrics

"ESD: Design and Synthesis" is a continuation of the author's series of books on ESD protection. It is an essential reference for: ESD, circuit, and semiconductor engineers; design synthesis team leaders; layout design, characterisation, floorplanning, test and reliability engineers; technicians; and groundrule and test site developers in the manufacturing and design of semiconductor chips.

It is also useful for graduate and undergraduate students in electrical engineering, semiconductor sciences, and manufacturing sciences, and on courses involving the design of ESD devices, chips and systems. This book offers a useful insight into the issues that confront modern technology as we enter the nano-electronic era.