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High-Level Power Analysis and Optimization (Hardcover, 1998 ed.): Anand Raghunathan, Niraj K. Jha, Sujit Dey High-Level Power Analysis and Optimization (Hardcover, 1998 ed.)
Anand Raghunathan, Niraj K. Jha, Sujit Dey
R2,961 Discovery Miles 29 610 Ships in 10 - 15 working days

High-Level Power Analysis and Optimization presents a comprehensive description of power analysis and optimization techniques at the higher (architecture and behavior) levels of the design hierarchy, which are often the levels that yield the most power savings. This book describes power estimation and optimization techniques for use during high-level (behavioral synthesis), as well as for designs expressed at the register-transfer or architecture level. High-Level Power Analysis and Optimization surveys the state-of-the-art research on the following topics: power estimation/macromodeling techniques for architecture-level designs, high-level power management techniques, and high-level synthesis optimizations for low power. High-Level Power Analysis and Optimization will be very useful reading for students, researchers, designers, design methodology developers, and EDA tool developers who are interested in low-power VLSI design or high-level design methodologies.

High-Level Power Analysis and Optimization (Paperback, Softcover reprint of the original 1st ed. 1998): Anand Raghunathan,... High-Level Power Analysis and Optimization (Paperback, Softcover reprint of the original 1st ed. 1998)
Anand Raghunathan, Niraj K. Jha, Sujit Dey
R2,776 Discovery Miles 27 760 Ships in 10 - 15 working days

High-Level Power Analysis and Optimization presents a comprehensive description of power analysis and optimization techniques at the higher (architecture and behavior) levels of the design hierarchy, which are often the levels that yield the most power savings. This book describes power estimation and optimization techniques for use during high-level (behavioral synthesis), as well as for designs expressed at the register-transfer or architecture level. High-Level Power Analysis and Optimization surveys the state-of-the-art research on the following topics: power estimation/macromodeling techniques for architecture-level designs, high-level power management techniques, and high-level synthesis optimizations for low power. High-Level Power Analysis and Optimization will be very useful reading for students, researchers, designers, design methodology developers, and EDA tool developers who are interested in low-power VLSI design or high-level design methodologies.

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