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In recent years, low power design has become one of the focuses of
digital VLSI circuits. As technology scales, leakage currents in
contemporary CMOS logic have become one of the main power
consumers. Contrary to conventional methods for power reduction,
operation of digital circuits in the subthreshold region minimizes
power consumption in low-frequency systems. This book presents
pre-layout and post-layout simulations of existing 8T Latch and
proposed latch designs in sub-threshold region. The proposed
circuits consist of pass transistor gate logic. Proposed designs
are area efficient so useful for portable devices. The proposed
designs remarkably reduce power consumption and delay hence reduces
power-delay product (PDP). Comparison with the existing design and
proposed latch designs are performed at 65nm and 45nm to show
technology independence. Comparative simulation results show that
proposed 7T latch design with delay is better choice for portable
applications. Therefore, the proposed 7T latch design with delay
proves to be a viable option for low power and energy efficient
applications.
Arithmetic circuits, like adders and multipliers, are one of the
basic components in the design of communication circuits. In fact
8.72% of all instructions in a typical scientific program are
multiplies. The multiplier is a fairly large block of a computing
system. Multiplier is not only a high-delay block but also a
significant source of power dissipation. That's why, if one also
aims to minimize power consumption, it is of great interest to
identify the techniques to be applied to reduce delay by using
various delay optimizations. Array architecture is a popular
technique to implement the multipliers due to its compact
structure. In this book, six array multiplier circuits using
different AND cells and XOR gates have been designed, simulated,
analyzed and compared. This analysis should help shed some light on
the low power and high throughput 2x2 array multiplier cells and
should be especially useful for post graduate students and research
scholars working in low power VLSI circuit design field."
The advancement of CMOS technologies paved the road for a growing
market of mobile and portable electronic devices. This growth is
driven by the continual integration of complex analog and digital
building blocks on a single chip, so silicon area and power
consumption are the two most valued aspects of the design. Compared
to static CMOS logic, dynamic logic offers good performance. Wide
fan-in logic such as domino circuits is used in high-performance
applications. Dynamic domino logic circuits are widely used in
modern digital VLSI circuits. These dynamic circuits are often
favored in high performance designs because of the speed advantage
offered over static CMOS logic circuits. In this dissertation, 2:1
multiplexer and 1:2 decoder is proposed. The proposed 2:1
multiplexer and 1:2 decoder design based on proposed high
performance domino logic circuit are tested in 45nm and 65nm
technologies to prove its technology independence. Design is also
experimented under various substrate-biasing schemes and then the
best substrate biasing technique is implemented. The proposed
design is better in terms of power, delay and power delay product
in comparison to other biasing conditions.
Full adder is an essential component for designing all types of
processors viz. digital signal processors (DSP), microprocessors
etc. In most of the digital systems adder lies in the critical path
that affects the overall speed of the system. So enhancing the
performance of the 1-bit full adder cell is of prime concern. This
book presents the general methodology to modify performance of full
adder by adding an extra transistor to the node causing loss. The
introduced design of full adder cell remarkably reduces power
consumption hence PDP, improves noise immunity and temperature
sustainability in comparison to the conventional design. All
simulations are performed on 45nm and 90nm standard models on
Tanned EDA tool version 12.6. This book, therefore, provides a new
metric of implementing high performance technology independent full
adder circuit and the Ripple Carry Adder as its application. The
analysis should help shed some light on the new and exciting
approach for achieving low power and high throughput adder cell and
should be especially useful to post graduate students and research
scholars in VLSI circuit design field.
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