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This book explores the design implications of emerging,
non-volatile memory (NVM) technologies on future computer memory
hierarchy architecture designs. Since NVM technologies combine the
speed of SRAM, the density of DRAM, and the non-volatility of Flash
memory, they are very attractive as the basis for future universal
memories. This book provides a holistic perspective on the topic,
covering modeling, design, architecture and applications. The
practical information included in this book will enable designers
to exploit emerging memory technologies to improve significantly
the performance/power/reliability of future, mainstream integrated
circuits.
The emerging three-dimensional (3D) chip architectures, with their
intrinsic capability of reducing the wire length, promise
attractive solutions to reduce the delay of interconnects in future
microprocessors. 3D memory stacking enables much higher memory
bandwidth for future chip-multiprocessor design, mitigating the
"memory wall" problem. In addition, heterogenous integration
enabled by 3D technology can also result in innovative designs for
future microprocessors. This book first provides a brief
introduction to this emerging technology, and then presents a
variety of approaches to designing future 3D microprocessor
systems, by leveraging the benefits of low latency, high bandwidth,
and heterogeneous integration capability which are offered by 3D
technology.
This book explores the design implications of emerging,
non-volatile memory (NVM) technologies on future computer memory
hierarchy architecture designs. Since NVM technologies combine the
speed of SRAM, the density of DRAM, and the non-volatility of Flash
memory, they are very attractive as the basis for future universal
memories. This book provides a holistic perspective on the topic,
covering modeling, design, architecture and applications. The
practical information included in this book will enable designers
to exploit emerging memory technologies to improve significantly
the performance/power/reliability of future, mainstream integrated
circuits.
We live in a time of great change. In the electronics world, the
last several decades have seen unprecedented growth and
advancement, described by Moore's law. This observation stated that
transistor density in integrated circuits doubles every 1. 5-2
years. This came with the simultaneous improvement of individual
device perf- mance as well as the reduction of device power such
that the total power of the resulting ICs remained under control.
No trend remains constant forever, and this is unfortunately the
case with Moore's law. The trouble began a number of years ago when
CMOS devices were no longer able to proceed along the classical
scaling trends. Key device parameters such as gate oxide thickness
were simply no longer able to scale. As a result, device o- state
currents began to creep up at an alarming rate. These continuing
problems with classical scaling have led to a leveling off of IC
clock speeds to the range of several GHz. Of course, chips can be
clocked higher but the thermal issues become unmanageable. This has
led to the recent trend toward microprocessors with mul- ple cores,
each running at a few GHz at the most. The goal is to continue
improving performance via parallelism by adding more and more cores
instead of increasing speed. The challenge here is to ensure that
general purpose codes can be ef?ciently parallelized. There is
another potential solution to the problem of how to improve CMOS
technology performance: three-dimensional integrated circuits (3D
ICs).
We live in a time of great change. In the electronics world, the
last several decades have seen unprecedented growth and
advancement, described by Moore's law. This observation stated that
transistor density in integrated circuits doubles every 1. 5-2
years. This came with the simultaneous improvement of individual
device perf- mance as well as the reduction of device power such
that the total power of the resulting ICs remained under control.
No trend remains constant forever, and this is unfortunately the
case with Moore's law. The trouble began a number of years ago when
CMOS devices were no longer able to proceed along the classical
scaling trends. Key device parameters such as gate oxide thickness
were simply no longer able to scale. As a result, device o- state
currents began to creep up at an alarming rate. These continuing
problems with classical scaling have led to a leveling off of IC
clock speeds to the range of several GHz. Of course, chips can be
clocked higher but the thermal issues become unmanageable. This has
led to the recent trend toward microprocessors with mul- ple cores,
each running at a few GHz at the most. The goal is to continue
improving performance via parallelism by adding more and more cores
instead of increasing speed. The challenge here is to ensure that
general purpose codes can be ef?ciently parallelized. There is
another potential solution to the problem of how to improve CMOS
technology performance: three-dimensional integrated circuits (3D
ICs).
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