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On Optimal Interconnections for VLSI (Paperback, Softcover reprint of the original 1st ed. 1995)
Loot Price: R4,232
Discovery Miles 42 320
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On Optimal Interconnections for VLSI (Paperback, Softcover reprint of the original 1st ed. 1995)
Series: The Springer International Series in Engineering and Computer Science, 301
Expected to ship within 10 - 15 working days
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On Optimal Interconnections for VLSI describes, from a geometric
perspective, algorithms for high-performance, high-density
interconnections during the global and detailed routing phases of
circuit layout. First, the book addresses area minimization, with a
focus on near-optimal approximation algorithms for minimum-cost
Steiner routing. In addition to practical implementations of recent
methods, the implications of recent results on spanning tree degree
bounds and the method of Zelikovsky are discussed. Second, the book
addresses delay minimization, starting with a discussion of
accurate, yet algorithmically tractable, delay models. Recent
minimum-delay constructions are highlighted, including provably
good cost-radius tradeoffs, critical-sink routing algorithms,
Elmore delay-optimal routing, graph Steiner arborescences, non-tree
routing, and wiresizing. Third, the book addresses skew
minimization for clock routing and prescribed-delay routing
formulations. The discussion starts with early matching-based
constructions and goes on to treat zero-skew routing with provably
minimum wirelength, as well as planar clock routing. Finally, the
book concludes with a discussion of multiple (competing)
objectives, i.e., how to optimize area, delay, skew, and other
objectives simultaneously. These techniques are useful when the
routing instance has heterogeneous resources or is highly
congested, as in FPGA routing, multi-chip packaging, and very dense
layouts. Throughout the book, the emphasis is on practical
algorithms and a complete self-contained development. On Optimal
Interconnections for VLSI will be of use to both circuit designers
(CAD tool users) as well as researchers and developers in the area
of performance-driven physical design.
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