|
Books > Professional & Technical > Energy technology & engineering > Electrical engineering
|
Buy Now
Optimal VLSI Architectural Synthesis - Area, Performance and Testability (Paperback, Softcover reprint of the original 1st ed. 1992)
Loot Price: R4,352
Discovery Miles 43 520
|
|
|
Optimal VLSI Architectural Synthesis - Area, Performance and Testability (Paperback, Softcover reprint of the original 1st ed. 1992)
Series: The Springer International Series in Engineering and Computer Science, 158
Expected to ship within 10 - 15 working days
|
Although research in architectural synthesis has been conducted for
over ten years it has had very little impact on industry. This in
our view is due to the inability of current architectural
synthesizers to provide area-delay competitive (or "optimal")
architectures, that will support interfaces to analog,
asynchronous, and other complex processes. They also fail to
incorporate testability. The OASIC (optimal architectural synthesis
with interface constraints) architectural synthesizer and the
CATREE (computer aided trees) synthesizer demonstrate how these
problems can be solved. Traditionally architectural synthesis is
viewed as NP hard and there fore most research has involved
heuristics. OASIC demonstrates by using an IP approach (using
polyhedral analysis), that most input algo rithms can be
synthesized very fast into globally optimal architectures. Since a
mathematical model is used, complex interface constraints can
easily be incorporated and solved. Research in test incorporation
has in general been separate from syn thesis research. This is due
to the fact that traditional test research has been at the gate or
lower level of design representation. Nevertheless as technologies
scale down, and complexity of design scales up, the push for
reducing testing times is increased. On way to deal with this is to
incorporate test strategies early in the design process. The second
half of this text examines an approach for integrating
architectural synthesis with test incorporation. Research showed
that test must be considered during synthesis to provide good
architectural solutions which minimize Xlll area delay cost
functions."
General
Is the information for this product incomplete, wrong or inappropriate?
Let us know about it.
Does this product have an incorrect or missing image?
Send us a new image.
Is this product missing categories?
Add more categories.
Review This Product
No reviews yet - be the first to create one!
|
You might also like..
|
Welcome to Loot.co.za!
Sign in / Register |Wishlists & Gift Vouchers |Help | Advanced search
