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High Level Synthesis of ASICs under Timing and Synchronization Constraints (Paperback, Softcover reprint of hardcover 1st ed. 1992)
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High Level Synthesis of ASICs under Timing and Synchronization Constraints (Paperback, Softcover reprint of hardcover 1st ed. 1992)
Series: The Springer International Series in Engineering and Computer Science, 177
Expected to ship within 18 - 22 working days
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Computer-aided synthesis of digital circuits from behavioral level
specifications offers an effective means to deal with increasing
complexity of digital hardware design. High Level Synthesis of
ASICs Under Timing and Synchronization Constraints addresses both
theoretical and practical aspects in the design of a high-level
synthesis system that transforms a behavioral level description of
hardware to a synchronous logic-level implementation consisting of
logic gates and registers. High Level Synthesis of ASICs Under
Timing and Synchronization Constraints addresses specific issues in
applying high-level synthesis techniques to the design of ASICs.
This complements previous results achieved in synthesis of
general-purpose and signal processors, where data-path design is of
utmost importance. In contrast, ASIC designs are often
characterized by complex control schemes, to support communication
and synchronization with the environment. The combined design of
efficient data-path control-unit is the major contribution of this
book. Three requirements are important in modeling ASIC designs:
concurrency, external synchronization, and detailed timing
constraints. The objective of the research work presented here is
to develop a hardware model incorporating these requirements as
well as synthesis algorithms that operate on this hardware model.
The contributions of this book address both the theory and the
implementation of algorithm for hardware synthesis.
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