Hierarchical Annotated Action Diagrams - An Interface-Oriented Specification and Verification Method (Paperback, Softcover reprint of the original 1st ed. 1998)

Standardization of hardware description languages and the availability of synthesis tools has brought about a remarkable increase in the productivity of hardware designers. Yet design verification methods and tools lag behind and have difficulty in dealing with the increasing design complexity. This may get worse because more complex systems are now constructed by (re)using Intellectual Property blocks developed by third parties. To verify such designs, abstract models of the blocks and the system must be developed, with separate concerns, such as interface communication, functionality, and timing, that can be verified in an almost independent fashion. Standard Hardware Description Languages such as VHDL and Verilog are inspired by procedural `imperative' programming languages in which function and timing are inherently intertwined in the statements of the language. Furthermore, they are not conceived to state the intent of the design in a simple declarative way that contains provisions for design choices, for stating assumptions on the environment, and for indicating uncertainty in system timing. Hierarchical Annotated Action Diagrams: An Interface-Oriented Specification and Verification Method presents a description methodology that was inspired by Timing Diagrams and Process Algebras, the so-called Hierarchical Annotated Diagrams. It is suitable for specifying systems with complex interface behaviors that govern the global system behavior. A HADD specification can be converted into a behavioral real-time model in VHDL and used to verify the surrounding logic, such as interface transducers. Also, function can be conservatively abstracted away and the interactions between interconnected devices can be verified using Constraint Logic Programming based on Relational Interval Arithmetic. Hierarchical Annotated Action Diagrams: An Interface-Oriented Specification and Verification Method is of interest to readers who are involved in defining methods and tools for system-level design specification and verification. The techniques for interface compatibility verification can be used by practicing designers, without any more sophisticated tool than a calculator.

General

Imprint:	Springer-Verlag New York
Country of origin:	United States
Release date:	October 2012
First published:	October 2012
Authors:	Eduard Cerny • Bachir Berkane • Pierre Girodias • Karim Khordoc
Dimensions:	235 x 155 x 12mm (L x W x T)
Format:	Paperback
Pages:	211
Edition:	Softcover reprint of the original 1st ed. 1998
ISBN-13:	978-1-4613-7569-2
Categories:	Books > Computing & IT > Computer hardware & operating systems > General Books > Professional & Technical > Technology: general issues > Technical design > Computer aided design (CAD) Books > Professional & Technical > Energy technology & engineering > Electrical engineering > General Books > Professional & Technical > Electronics & communications engineering > Electronics engineering > Circuits & components Books > Computing & IT > Applications of computing > Artificial intelligence > General Promotions
LSN:	1-4613-7569-X
Barcode:	9781461375692

Is the information for this product incomplete, wrong or inappropriate? Let us know about it.

Does this product have an incorrect or missing image? Send us a new image.

Is this product missing categories? Add more categories.

Review This Product

No reviews yet - be the first to create one!