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Formal Verification - An Essential Toolkit for Modern VLSI Design (Paperback, 2nd edition)
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Formal Verification - An Essential Toolkit for Modern VLSI Design (Paperback, 2nd edition)
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Formal Verification: An Essential Toolkit for Modern VLSI Design,
Second Edition presents practical approaches for design and
validation, with hands-on advice to help working engineers
integrate these techniques into their work. Formal Verification
(FV) enables a designer to directly analyze and mathematically
explore the quality or other aspects of a Register Transfer Level
(RTL) design without using simulations. This can reduce time spent
validating designs and more quickly reach a final design for
manufacturing. Building on a basic knowledge of SystemVerilog, this
book demystifies FV and presents the practical applications that
are bringing it into mainstream design and validation processes.
New sections cover advanced techniques, and a new chapter, The Road
To Formal Signoff, emphasizes techniques used when replacing
simulation work with Formal Verification. After reading this book,
readers will be prepared to introduce FV in their organization to
effectively deploy FV techniques that increase design and
validation productivity.
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