Logic Synthesis and Verification Algorithms (Paperback, Softcover reprint of the original 1st ed. 1996)

Logic Synthesis and Verification Algorithms is a textbook designed for courses on VLSI Logic Synthesis and Verification, Design Automation, CAD and advanced level discrete mathematics. It also serves as a basic reference work in design automation for both professionals and students. Logic Synthesis and Verification Algorithms is about the theoretical underpinnings of VLSI (Very Large Scale Integrated Circuits). It combines and integrates modern developments in logic synthesis and formal verification with the more traditional matter of Switching and Finite Automata Theory. The book also provides background material on Boolean algebra and discrete mathematics. A unique feature of this text is the large collection of solved problems. Throughout the text the algorithms covered are the subject of one or more problems based on the use of available synthesis programs.

General

Imprint:	Springer-Verlag New York
Country of origin:	United States
Release date:	March 2013
First published:	1996
Authors:	Gary D. Hachtel • Fabio Somenzi
Dimensions:	254 x 178 x 31mm (L x W x T)
Format:	Paperback
Pages:	564
Edition:	Softcover reprint of the original 1st ed. 1996
ISBN-13:	978-1-4757-7036-0
Categories:	Books > Science & Mathematics > Mathematics > General Books > Computing & IT > Computer programming > General Books > Professional & Technical > Technology: general issues > Technical design > Computer aided design (CAD) Books > Professional & Technical > Energy technology & engineering > Electrical engineering > General Books > Professional & Technical > Electronics & communications engineering > Electronics engineering > Circuits & components Books > Computing & IT > Applications of computing > Artificial intelligence > General
LSN:	1-4757-7036-7
Barcode:	9781475770360

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