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Writing Testbenches - Functional Verification of HDL Models (Paperback, Softcover reprint of the original 1st ed. 2002)
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Writing Testbenches - Functional Verification of HDL Models (Paperback, Softcover reprint of the original 1st ed. 2002)
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Writing Testbenches: Functional Verification of HDL Models first
introduces the necessary concepts and tools of verification, then
describes a process for carrying out an effective functional
verification of a design. This book also presents techniques for
applying a stimulus and monitoring the response of a design by
abstracting the operations using bus-functional models. The
architecture of testbenches built around these bus-functional
models is important for minimizing development and maintenance
effort. Behavioral modeling is another important concept presented
in this book. It is used to parallelize the implementation and
verification of a design and to perform more efficient simulations.
For many, behavioral modeling is synonymous with synthesizeable or
RTL modeling. In this book, the term 'behavioural' is used to
describe any model that adequately emulates the functionality of a
design, usually using non-synthesizeable constructs and coding
style. Writing Testbenches: Functional Verification of HDL Models
focuses on the functional verification of hardware designs using
either VHDL or Verilog.The reader should have at least a basic
knowledge of one of the languages. Ideally, he or she should have
experience in writing synthesizeable models and be familiar with
running a simulation using any of the available VHDL or Verilog
simulators. From the Foreword 'With gate counts and system
complexity growing exponentially, engineers confront the most
perplexing challenge in product design: functional verification.
The bulk of the time consumed in the design of new ICs and systems
is now spent on verification. New and interesting design
technologies like physical synthesis and design reuse that create
ever- larger designs only aggravate the problem. What the EDA tool
industry has continuously failed to realize is that the real
problem is not how to create a 12 million gate IC that runs at 600
MHz, but how to verify it. This text marks the first genuine effort
at defining a verification methodology that is independent of both
tools and applications. Engineers now have a true reference text
for quickly and accurately verifying the functionality of their
designs.' Michael Horne, President and CEO, Qualis Design
Corporation
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