Robust SRAM Designs and Analysis (Paperback, 2013 ed.)

Jawar Singh, Saraju P. Mohanty, Dhiraj K. Pradhan

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This book provides a guide to Static Random Access Memory (SRAM) bitcell design and analysis to meet the nano-regime challenges for CMOS devices and emerging devices, such as Tunnel FETs. Since process variability is an ongoing challenge in large memory arrays, this book highlights the most popular SRAM bitcell topologies (benchmark circuits) that mitigate variability, along with exhaustive analysis. Experimental simulation setups are also included, which cover nano-regime challenges such as process variation, leakage and NBTI for SRAM design and analysis. Emphasis is placed throughout the book on the various trade-offs for achieving a best SRAM bitcell design. Provides a complete and concise introduction to SRAM bitcell design and analysis; Offers techniques to face nano-regime challenges such as process variation, leakage and NBTI for SRAM design and analysis; Includes simulation set-ups for extracting different design metrics for CMOS technology and emerging devices; Emphasizes different trade-offs for achieving the best possible SRAM bitcell design.

General

Imprint:	Springer-Verlag New York
Country of origin:	United States
Release date:	August 2014
First published:	2013
Authors:	Jawar Singh • Saraju P. Mohanty • Dhiraj K. Pradhan
Dimensions:	235 x 155 x 10mm (L x W x T)
Format:	Paperback
Pages:	168
Edition:	2013 ed.
ISBN-13:	978-1-4939-0244-6
Categories:	Books > Professional & Technical > Electronics & communications engineering > Electronics engineering > Circuits & components Books > Professional & Technical > Industrial chemistry & manufacturing technologies > Other manufacturing technologies > Precision instruments manufacture > General
LSN:	1-4939-0244-X
Barcode:	9781493902446