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Digital Timing Macromodeling for VLSI Design Verification (Paperback, Softcover reprint of the original 1st ed. 1995)
Loot Price: R4,011
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Digital Timing Macromodeling for VLSI Design Verification (Paperback, Softcover reprint of the original 1st ed. 1995)
Series: The Springer International Series in Engineering and Computer Science, 319
Expected to ship within 18 - 22 working days
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Digital Timing Macromodeling for VLSI Design Verification first of
all provides an extensive history of the development of simulation
techniques. It presents detailed discussion of the various
techniques implemented in circuit, timing, fast-timing,
switch-level timing, switch-level, and gate-level simulation. It
also discusses mixed-mode simulation and interconnection analysis
methods. The review in Chapter 2 gives an understanding of the
advantages and disadvantages of the many techniques applied in
modern digital macromodels. The book also presents a wide variety
of techniques for performing nonlinear macromodeling of digital MOS
subcircuits which address a large number of shortcomings in
existing digital MOS macromodels. Specifically, the techniques
address the device model detail, transistor coupling capacitance,
effective channel length modulation, series transistor reduction,
effective transconductance, input terminal dependence, gate
parasitic capacitance, the body effect, the impact of parasitic
RC-interconnects, and the effect of transmission gates. The
techniques address major sources of errors in existing
macromodeling techniques, which must be addressed if macromodeling
is to be accepted in commercial CAD tools by chip designers. The
techniques presented in Chapters 4-6 can be implemented in other
macromodels, and are demonstrated using the macromodel presented in
Chapter 3. The new techniques are validated over an extremely wide
range of operating conditions: much wider than has been presented
for previous macromodels, thus demonstrating the wide range of
applicability of these techniques.
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