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From Contamination to Defects, Faults and Yield Loss - Simulation and Applications (Hardcover, 1996 ed.)
Loot Price: R3,119
Discovery Miles 31 190
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From Contamination to Defects, Faults and Yield Loss - Simulation and Applications (Hardcover, 1996 ed.)
Series: Frontiers in Electronic Testing, 5
Expected to ship within 10 - 15 working days
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Over the years there has been a large increase in the functionality
available on a single integrated circuit. This has been mainly
achieved by a continuous drive towards smaller feature sizes,
larger dies, and better packing efficiency. However, this greater
functionality has also resulted in substantial increases in the
capital investment needed to build fabrication facilities. Given
such a high level of investment, it is critical for IC
manufacturers to reduce manufacturing costs and get a better return
on their investment. The most obvious method of reducing the
manufacturing cost per die is to improve manufacturing yield.
Modern VLSI research and engineering (which includes design
manufacturing and testing) encompasses a very broad range of
disciplines such as chemistry, physics, material science, circuit
design, mathematics and computer science. Due to this diversity,
the VLSI arena has become fractured into a number of separate
sub-domains with little or no interaction between them. This is the
case with the relationships between testing and manufacturing. From
Contamination to Defects, Faults and Yield Loss: Simulation and
Applications focuses on the core of the interface between
manufacturing and testing, i.e., the contamination-defect-fault
relationship. The understanding of this relationship can lead to
better solutions of many manufacturing and testing problems.
Failure mechanism models are developed and presented which can be
used to accurately estimate probability of different failures for a
given IC. This information is critical in solving key yield-related
applications such as failure analysis, fault modeling and design
manufacturing.
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