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Computer-Aided Design Techniques for Low Power Sequential Logic Circuits (Paperback, Softcover reprint of the original 1st ed. 1997)
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Computer-Aided Design Techniques for Low Power Sequential Logic Circuits (Paperback, Softcover reprint of the original 1st ed. 1997)
Series: The Springer International Series in Engineering and Computer Science, 387
Expected to ship within 10 - 15 working days
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Rapid increases in chip complexity, increasingly faster clocks, and
the proliferation of portable devices have combined to make power
dissipation an important design parameter. The power consumption of
a digital system determines its heat dissipation as well as battery
life. For some systems, power has become the most critical design
constraint. Computer-Aided Design Techniques for Low Power
Sequential Logic Circuits presents a methodology for low power
design. The authors first present a survey of techniques for
estimating the average power dissipation of a logic circuit. At the
logic level, power dissipation is directly related to average
switching activity. A symbolic simulation method that accurately
computes the average switching activity in logic circuits is then
described. This method is extended to handle sequential logic
circuits by modeling correlation in time and by calculating the
probabilities of present state lines. Computer-Aided Design
Techniques for Low Power Sequential Logic Circuits then presents a
survey of methods to optimize logic circuits for low power
dissipation which target reduced switching activity. A method to
retime a sequential logic circuit where registers are repositioned
such that the overall glitching in the circuit is minimized is also
described. The authors then detail a powerful optimization method
that is based on selectively precomputing the output logic values
of a circuit one clock cycle before they are required, and using
the precomputed value to reduce internal switching activity in the
succeeding clock cycle. Presented next is a survey of methods that
reduce switching activity in circuits described at the
register-transfer and behavioral levels. Also described is a
scheduling algorithm that reduces power dissipation by maximising
the inactivity period of the modules in a given circuit.
Computer-Aided Design Techniques for Low Power Sequential Logic
Circuits concludes with a summary and directions for future
research.
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