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Formal Semantics and Proof Techniques for Optimizing VHDL Models (Paperback, Softcover reprint of the original 1st ed. 1999) Loot Price: R2,756
Discovery Miles 27 560
Repayment Terms: R258 pm x 12*
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Formal Semantics and Proof Techniques for Optimizing VHDL Models (Paperback, Softcover reprint of the original 1st ed. 1999):...

Formal Semantics and Proof Techniques for Optimizing VHDL Models (Paperback, Softcover reprint of the original 1st ed. 1999)

Kothanda Umamageswaran, Sheetanshu L. Pandey, Philip A. Wilsey

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Loot Price R2,756 Discovery Miles 27 560 | Repayment Terms: R258 pm x 12*

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Written expressly for hardware designers, this book presents a formal model of VHDL clearly specifying both the static and dynamic semantics of VHDL. It provides a mathematical framework for representing VHDL constructs and shows how those constructs can be formally manipulated to reason about VHDL.

General

Imprint: Springer-Verlag New York
Country of origin: United States
Release date: October 2012
First published: October 2012
Authors: Kothanda Umamageswaran • Sheetanshu L. Pandey • Philip A. Wilsey
Dimensions: 235 x 155 x 9mm (L x W x T)
Format: Paperback
Pages: 158
Edition: Softcover reprint of the original 1st ed. 1999
ISBN-13: 978-1-4613-7331-5
Categories: Books > Computing & IT > Computer hardware & operating systems > General
Books > Professional & Technical > Technology: general issues > Technical design > Computer aided design (CAD)
Books > Professional & Technical > Energy technology & engineering > Electrical engineering > General
Books > Professional & Technical > Electronics & communications engineering > Electronics engineering > Circuits & components
LSN: 1-4613-7331-X
Barcode: 9781461373315

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