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Embedded Multiprocessor System-on-Chip for Access Network Processing (Paperback)
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Embedded Multiprocessor System-on-Chip for Access Network Processing (Paperback)
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Master's Thesis from the year 2007 in the subject Computer Science
- Applied, grade: 1.0, Technical University of Munich (Institute
for Informatics), 82 entries in the bibliography, language:
English, abstract: Multicore systems are dominating the processor
market; they enable the increase in computing power of a single
chip in proportion to the Moore's law-driven increase in number of
transistors. A similar evolution is observed in the system-on-chip
(SoC) market through the emergence of multi-processor SoC (MPSoC)
designs. Nevertheless, MPSoCs introduce some challenges to the
system architects concerning the efficient design of memory
hierarchies and system interconnects while maintaining the low
power and cost constraints. In this master thesis, I try to address
some of these challenges: namely, non-cache coherent DMA transfers
in MPSoCs, low instruction cache utilization by OS codes, and
factors governing the system throughput in MPSoC designs. These
issues are investigated using the empirical and simulation
approaches. Empirical studies are conducted on the Danube platform.
Danube is a commercial MPSoC platform that is based on two 32-bit
MIPS cores and developed by Infineon Technologies AG for deployment
in access network processing equipments such as integrated access
devices, customer premises equipments, and home gateways.
Simulation-based studies are conducted on a system based on the ARM
MPCore architecture. Achievements include the successful
implementation and testing of novel hardware and software solutions
for improving the performance of non-cache coherent DMA transfers
in MPSoCs. Several techniques for reducing the instruction cache
miss rate are investigated and applied. Finally, a qualitative
analysis of the impact of instruction reuse, number of cores, and
memory bandwidth on the system throughput in MPSoC systems is
presented.
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