High definition video requires substantial compression in order
to be transmitted or stored economically. Advances in video coding
standards from MPEG-1, MPEG-2, MPEG-4 to H.264/AVC have provided
ever increasing coding efficiency, at the expense of great
computational complexity which can only be delivered through
massively parallel processing.
This book will present VLSI architectural design and chip
implementation for high definition H.264/AVC video encoding, using
a state-of-the-art video application, with complete VLSI prototype,
via FPGA/ASIC. It will serve as an invaluable reference for anyone
interested in VLSI design and high-level (EDA) synthesis for
video.
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