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Digital System Test and Testable Design - Using HDL Models and Architectures (Hardcover, 2011 ed.)
Loot Price: R3,538
Discovery Miles 35 380
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Digital System Test and Testable Design - Using HDL Models and Architectures (Hardcover, 2011 ed.)
Expected to ship within 10 - 15 working days
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This book is about digital system testing and testable design. The
concepts of testing and testability are treated together with
digital design practices and methodologies. The book uses Verilog
models and testbenches for implementing and explaining fault
simulation and test generation algorithms. Extensive use of Verilog
and Verilog PLI for test applications is what distinguishes this
book from other test and testability books. Verilog eliminates
ambiguities in test algorithms and BIST and DFT hardware
architectures, and it clearly describes the architecture of the
testability hardware and its test sessions. Describing many of the
on-chip decompression algorithms in Verilog helps to evaluate these
algorithms in terms of hardware overhead and timing, and thus
feasibility of using them for System-on-Chip designs. Extensive use
of testbenches and testbench development techniques is another
unique feature of this book. Using PLI in developing testbenches
and virtual testers provides a powerful programming tool,
interfaced with hardware described in Verilog. This mixed
hardware/software environment facilitates description of complex
test programs and test strategies.
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