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Low-Power High-Speed ADCs for Nanometer CMOS Integration (Paperback, Softcover reprint of hardcover 1st ed. 2008) Loot Price: R2,736
Discovery Miles 27 360
Low-Power High-Speed ADCs for Nanometer CMOS Integration (Paperback, Softcover reprint of hardcover 1st ed. 2008): Zhiheng Cao,...

Low-Power High-Speed ADCs for Nanometer CMOS Integration (Paperback, Softcover reprint of hardcover 1st ed. 2008)

Zhiheng Cao, Shouli Yan

Series: Analog Circuits and Signal Processing

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Loot Price R2,736 Discovery Miles 27 360 | Repayment Terms: R256 pm x 12*

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Low-Power High-Speed ADCs for Nanometer CMOS Integration is about the design and implementation of ADC in nanometer CMOS processes that achieve lower power consumption for a given speed and resolution than previous designs, through architectural and circuit innovations that take advantage of unique features of nanometer CMOS processes. A phase lock loop (PLL) clock multiplier has also been designed using new circuit techniques and successfully tested. 1) A 1.2V, 52mW, 210MS/s 10-bit two-step ADC in 130nm CMOS occupying 0.38mm2. Using offset canceling comparators and capacitor networks implemented with small value interconnect capacitors to replace resistor ladder/multiplexer in conventional sub-ranging ADCs, it achieves 74dB SFDR for 10MHz and 71dB SFDR for 100MHz input. 2) A 32mW, 1.25GS/s 6-bit ADC with 2.5GHz internal clock in 130nm CMOS. A new type of architecture that combines flash and SAR enables the lowest power consumption, 6-bit >1GS/s ADC reported to date. This design can be a drop-in replacement for existing flash ADCs since it does require any post-processing or calibration step and has the same latency as flash. 3) A 0.4ps-rms-jitter (integrated from 3kHz to 300MHz offset for >2.5GHz) 1-3GHz tunable, phase-noise programmable clock-multiplier PLL for generating sampling clock to the SAR ADC. A new loop filter structure enables phase error preamplification to lower PLL in-band noise without increasing loop filter capacitor size.

General

Imprint: Springer
Country of origin: Netherlands
Series: Analog Circuits and Signal Processing
Release date: November 2010
First published: 2008
Authors: Zhiheng Cao • Shouli Yan
Dimensions: 235 x 155 x 5mm (L x W x T)
Format: Paperback
Pages: 95
Edition: Softcover reprint of hardcover 1st ed. 2008
ISBN-13: 978-90-481-7885-8
Categories: Books > Professional & Technical > Energy technology & engineering > General
Books > Professional & Technical > Electronics & communications engineering > Electronics engineering > Circuits & components
LSN: 90-481-7885-1
Barcode: 9789048178858

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