As the feature size decreases in deep sub-micron designs, coupling capacitance becomes the dominant factor in total capacitance. The resulting crosstalk noise may be responsible for signal integrity issues and significant timing variation. Traditionally, static timing analysis tools have ignored cross coupling effects between wires altogether. Newer tools simply approximate the coupling capacitance by a 2X Miller factor in order to compute the worst case delay. The latter approach not only reduces delay calculation accuracy, but can also be shown to underestimate the delay in certain scenarios. This book describes accurate but conservative methods for computing delay variation due to coupling. Furthermore, most of these methods are computationally efficient enough to be employed in a static timing analysis tool for complex integrated digital circuits. To achieve accuracy, a more accurate computation of the Miller factor is derived. To achieve both computational efficiency and accuracy, a variety of mechanisms for pruning the search space are detailed, including: -Spatial pruning - reducing aggressors to those in physical proximity, -Electrical pruning - reducing aggressors by electrical strength, -Temporal pruning - reducing aggressors using timing windows, -Functional pruning - reducing aggressors by Boolean functional analysis.

by Kurt Keutzer Those looking for a quick overview of the book should fast-forward to the Introduction in Chapter 1. What follows is a personal account of the creation of this book. The challenge from Earl Killian, formerly an architect of the MIPS processors and at that time Chief Architect at Tensilica, was to explain the significant performance gap between ASICs and custom circuits designed in the same process generation. The relevance of the challenge was amplified shortly thereafter by Andy Bechtolsheim, founder of Sun Microsystems and ubiquitous investor in the EDA industry. At a dinner talk at the 1999 International Symposium on Physical Design, Andy stated that the greatest near-term opportunity in CAD was to develop tools to bring the performance of ASIC circuits closer to that of custom designs. There seemed to be some synchronicity that two individuals so different in concern and character would be pre-occupied with the same problem. Intrigued by Earl and Andy's comments, the game was afoot. Earl Killian and other veterans of microprocessor design were helpful with clues as to the sources of the performance discrepancy: layout, circuit design, clocking methodology, and dynamic logic. I soon realized that I needed help in tracking down clues. Only at a wonderful institution like the University of California at Berkeley could I so easily commandeer an ab- bodied graduate student like David Chinnery with a knowledge of architecture, circuits, computer-aided design and algorithms.

This book describes a system of VLSI layout tools called IDA which stands for "Integrated Design Aides. " It is not a main-line production CAD environment, but neither is it a paper tool. Rather, IDA is an experimental environment that serves to test out CAD ideas in the crucible of real chip design. Many features have been tried in IDA over the years, some successfully, some not. This book will emphasize the former, and attempt to describe the features that have been useful and effective in building real chips. Before discussing the present state of IDA, it may be helpful to understand how the project got started. Although Bell Labs has traditionally had a large and effective effort in VLSI and CAD, researchers at the Murray Hill facility wanted to study the process of VLSI design independently, emphasizing the idea of small team chip building. So, in 1979 they invited Carver Mead to present his views on MOS chip design, complete with the now famous "lambda" design rules and "tall, thin designers. " To support this course, Steve Johnson (better known for YACC and the portable C compiler) and Sally Browning invented the constraint based "i" language and wrote a compiler for it. A small collection of layout tools developed rapidly around this compiler, including design rule checkers, editors and simulators."

This book carefully details design tools and techniques for realizing low power and energy efficiency in a highly productive design methodology.

Important topics include:
- Microarchitectural techniques to reduce energy per operation
- Power reduction with timing slack from pipelining
- Analysis of the benefits of using multiple supply and threshold voltages
- Placement techniques for multiple supply voltages
- Verification for multiple voltage domains
- Improved algorithms for gate sizing, and assignment of supply and threshold voltages
- Power gating design automation to reduce leakage
- Relationships among tatistical timing, power analysis, and parametric yield optimization

Design examples illustrate that these techniques can improve energy efficiency by two to three times.

An increasing number of system designers are using ASIP 's rather than ASIC 's to implement their system solutions. Building ASIPs: The Mescal Methodology gives a simple but comprehensive methodology for the design of these application-specific instruction processors (ASIPs).

The key elements of this methodology are:

Judiciously using benchmarking

Inclusively identifying the architectural space

Efficiently describing and evaluating the ASIPs

Comprehensively exploring the design space

Successfully deploying the ASIP

This book includes demonstrations of applications of the methodologies using the Tipi research framework as well as state-of-the-art commercial toolsets from CoWare and Tensilica.

Explains how to use low power design in an automated design flow, and examine the design time and performance trade-offs

Includes the latest tools and techniques for low power design applied in an ASIC design flow

Focuses on low power in an automated design methodology, a much neglected area

An increasing number of system designers are using ASIP 's rather than ASIC 's to implement their system solutions. Building ASIPs: The Mescal Methodology gives a simple but comprehensive methodology for the design of these application-specific instruction processors (ASIPs).

The key elements of this methodology are:

Judiciously using benchmarking

Inclusively identifying the architectural space

Efficiently describing and evaluating the ASIPs

Comprehensively exploring the design space

Successfully deploying the ASIP

This book includes demonstrations of applications of the methodologies using the Tipi research framework as well as state-of-the-art commercial toolsets from CoWare and Tensilica.

As the feature size decreases in deep sub-micron designs, coupling capacitance becomes the dominant factor in total capacitance. The resulting crosstalk noise may be responsible for signal integrity issues and significant timing variation. Traditionally, static timing analysis tools have ignored cross coupling effects between wires altogether. Newer tools simply approximate the coupling capacitance by a 2X Miller factor in order to compute the worst case delay. The latter approach not only reduces delay calculation accuracy, but can also be shown to underestimate the delay in certain scenarios.
This book describes accurate but conservative methods for computing delay variation due to coupling. Furthermore, most of these methods are computationally efficient enough to be employed in a static timing analysis tool for complex integrated digital circuits. To achieve accuracy, a more accurate computation of the Miller factor is derived. To achieve both computational efficiency and accuracy, a variety of mechanisms for pruning the search space are detailed, including:

-Spatial pruning - reducing aggressors to those in physical proximity,
-Electrical pruning - reducing aggressors by electrical strength,
-Temporal pruning - reducing aggressors using timing windows,
-Functional pruning - reducing aggressors by Boolean functional analysis.

by Kurt Keutzer Those looking for a quick overview of the book should fast-forward to the Introduction in Chapter 1. What follows is a personal account of the creation of this book. The challenge from Earl Killian, formerly an architect of the MIPS processors and at that time Chief Architect at Tensilica, was to explain the significant performance gap between ASICs and custom circuits designed in the same process generation. The relevance of the challenge was amplified shortly thereafter by Andy Bechtolsheim, founder of Sun Microsystems and ubiquitous investor in the EDA industry. At a dinner talk at the 1999 International Symposium on Physical Design, Andy stated that the greatest near-term opportunity in CAD was to develop tools to bring the performance of ASIC circuits closer to that of custom designs. There seemed to be some synchronicity that two individuals so different in concern and character would be pre-occupied with the same problem. Intrigued by Earl and Andy's comments, the game was afoot. Earl Killian and other veterans of microprocessor design were helpful with clues as to the sources of the performance discrepancy: layout, circuit design, clocking methodology, and dynamic logic. I soon realized that I needed help in tracking down clues. Only at a wonderful institution like the University of California at Berkeley could I so easily commandeer an ab- bodied graduate student like David Chinnery with a knowledge of architecture, circuits, computer-aided design and algorithms.