0
Your cart

Your cart is empty

Browse All Departments
  • All Departments
Price
  • R2,500 - R5,000 (2)
  • -
Status
Brand

Showing 1 - 2 of 2 matches in All Departments

Quick-Turnaround ASIC Design in VHDL - Core-Based Behavioral Synthesis (Hardcover, 1996 ed.): N. Bouden-Romdhane, Vijay... Quick-Turnaround ASIC Design in VHDL - Core-Based Behavioral Synthesis (Hardcover, 1996 ed.)
N. Bouden-Romdhane, Vijay Madisetti, J. W. Hines
R4,341 Discovery Miles 43 410 Ships in 10 - 15 working days

From the Foreword..... Modern digital signal processing applications provide a large challenge to the system designer. Algorithms are becoming increasingly complex, and yet they must be realized with tight performance constraints. Nevertheless, these DSP algorithms are often built from many constituent canonical subtasks (e.g., IIR and FIR filters, FFTs) that can be reused in other subtasks. Design is then a problem of composing these core entities into a cohesive whole to provide both the intended functionality and the required performance. In order to organize the design process, there have been two major approaches. The top-down approach starts with an abstract, concise, functional description which can be quickly generated. On the other hand, the bottom-up approach starts from a detailed low-level design where performance can be directly assessed, but where the requisite design and interface detail take a long time to generate. In this book, the authors show a way to effectively resolve this tension by retaining the high-level conciseness of VHDL while parameterizing it to get good fit to specific applications through reuse of core library components. Since they build on a pre-designed set of core elements, accurate area, speed and power estimates can be percolated to high- level design routines which explore the design space. Results are impressive, and the cost model provided will prove to be very useful. Overall, the authors have provided an up-to-date approach, doing a good job at getting performance out of high-level design. The methodology provided makes good use of extant design tools, and is realistic in terms of the industrial design process. The approach is interesting in its own right, but is also of direct utility, and it will give the existing DSP CAD tools a highly competitive alternative. The techniques described have been developed within ARPAs RASSP (Rapid Prototyping of Application Specific Signal Processors) project, and should be of great interest there, as well as to many industrial designers. Professor Jonathan Allen, Massachusetts Institute of Technology

Quick-Turnaround ASIC Design in VHDL - Core-Based Behavioral Synthesis (Paperback, Softcover reprint of the original 1st ed.... Quick-Turnaround ASIC Design in VHDL - Core-Based Behavioral Synthesis (Paperback, Softcover reprint of the original 1st ed. 1996)
N. Bouden-Romdhane, Vijay Madisetti, J. W. Hines
R4,201 Discovery Miles 42 010 Ships in 10 - 15 working days

From the Foreword..... Modern digital signal processing applications provide a large challenge to the system designer. Algorithms are becoming increasingly complex, and yet they must be realized with tight performance constraints. Nevertheless, these DSP algorithms are often built from many constituent canonical subtasks (e.g., IIR and FIR filters, FFTs) that can be reused in other subtasks. Design is then a problem of composing these core entities into a cohesive whole to provide both the intended functionality and the required performance. In order to organize the design process, there have been two major approaches. The top-down approach starts with an abstract, concise, functional description which can be quickly generated. On the other hand, the bottom-up approach starts from a detailed low-level design where performance can be directly assessed, but where the requisite design and interface detail take a long time to generate. In this book, the authors show a way to effectively resolve this tension by retaining the high-level conciseness of VHDL while parameterizing it to get good fit to specific applications through reuse of core library components. Since they build on a pre-designed set of core elements, accurate area, speed and power estimates can be percolated to high- level design routines which explore the design space. Results are impressive, and the cost model provided will prove to be very useful. Overall, the authors have provided an up-to-date approach, doing a good job at getting performance out of high-level design. The methodology provided makes good use of extant design tools, and is realistic in terms of the industrial design process. The approach is interesting in its own right, but is also of direct utility, and it will give the existing DSP CAD tools a highly competitive alternative. The techniques described have been developed within ARPAs RASSP (Rapid Prototyping of Application Specific Signal Processors) project, and should be of great interest there, as well as to many industrial designers. Professor Jonathan Allen, Massachusetts Institute of Technology

Free Delivery
Pinterest Twitter Facebook Google+
You may like...
Harry Potter Wizard Wand - In…
 (3)
R800 Discovery Miles 8 000
Jabra Elite 5 Hybrid ANC True Wireless…
R2,899 R2,245 Discovery Miles 22 450
Dig & Discover: Dinosaurs - Excavate 2…
Hinkler Pty Ltd Kit R256 Discovery Miles 2 560
Cadac Mantles (300 CP D/T) (3 / Blister…
R121 Discovery Miles 1 210
Varta V23 Professional Lithium Battery
R24 Discovery Miles 240
Atmosfire
Jan Braai Hardcover R590 R425 Discovery Miles 4 250
Cadac Pizza Stone (33cm)
 (18)
R398 Discovery Miles 3 980
Sony PlayStation Portal Remote Player…
R5,299 Discovery Miles 52 990
Cable Guy Ikon "Light Up" PlayStation…
R543 Discovery Miles 5 430
Bantex @School 13cm Kids Blunt Nose…
R16 Discovery Miles 160

 

Partners