0
Your cart

Your cart is empty

Browse All Departments
  • All Departments
Price
  • R2,500 - R5,000 (14)
  • -
Status
Brand

Showing 1 - 14 of 14 matches in All Departments

Direct Transistor-Level Layout for Digital Blocks (Paperback, Softcover reprint of the original 1st ed. 2004): Prakash... Direct Transistor-Level Layout for Digital Blocks (Paperback, Softcover reprint of the original 1st ed. 2004)
Prakash Gopalakrishnan, Rob A. Rutenbar
R2,955 Discovery Miles 29 550 Ships in 10 - 15 working days

Cell-based design methodologies have dominated layout generation of digital circuits. Unfortunately, the growing demands for transparent process portability, increased performance, and low-level device sizing for timing/power are poorly handled in a fixed cell library. Direct Transistor-Level Layout For Digital Blocks proposes a direct transistor-level layout approach for small blocks of custom digital logic as an alternative that better accommodates demands for device-level flexibility. This approach captures essential shape-level optimizations, yet scales easily to netlists with thousands of devices, and incorporates timing optimization during layout. The key idea is early identification of essential diffusion-merged MOS device groups, and their preservation in an uncommitted geometric form until the very end of detailed placement. Roughly speaking, essential groups are extracted early from the transistor-level netlist, placed globally, optimized locally, and then finally committed each to a specific shape-level form while concurrently optimizing for both density and routability. The essential flaw in prior efforts is an over-reliance on geometric assumptions from large-scale cell-based layout algorithms. Individual transistors may seem simple, but they do not pack as gates do. Algorithms that ignore these shape-level issues suffer the consequences when thousands of devices are poorly packed. The approach described in this book can pack devices much more densely than a typical cell-based layout. Direct Transistor-Level Layout For Digital Blocks is a comprehensive reference work on device-level layout optimization, which will be valuable to CAD tool and circuit designers.

Extreme Statistics in Nanoscale Memory Design (Paperback, 2010 ed.): Amith Singhee, Rob A. Rutenbar Extreme Statistics in Nanoscale Memory Design (Paperback, 2010 ed.)
Amith Singhee, Rob A. Rutenbar
R4,557 Discovery Miles 45 570 Ships in 10 - 15 working days

Knowledge exists: you only have to ?nd it VLSI design has come to an important in?ection point with the appearance of large manufacturing variations as semiconductor technology has moved to 45 nm feature sizes and below. If we ignore the random variations in the manufacturing process, simulation-based design essentially becomes useless, since its predictions will be far from the reality of manufactured ICs. On the other hand, using design margins based on some traditional notion of worst-case scenarios can force us to sacri?ce too much in terms of power consumption or manufacturing cost, to the extent of making the design goals even infeasible. We absolutely need to explicitly account for the statistics of this random variability, to have design margins that are accurate so that we can ?nd the optimum balance between yield loss and design cost. This discontinuity in design processes has led many researchers to develop effective methods of statistical design, where the designer can simulate not just the behavior of the nominal design, but the expected statistics of the behavior in manufactured ICs. Memory circuits tend to be the hardest hit by the problem of these random variations because of their high replication count on any single chip, which demands a very high statistical quality from the product. Requirements of 5-6s (0.

Practical Synthesis of High-Performance Analog Circuits (Paperback, Softcover reprint of the original 1st ed. 1998): Emil S.... Practical Synthesis of High-Performance Analog Circuits (Paperback, Softcover reprint of the original 1st ed. 1998)
Emil S. Ochotta, Tamal Mukherjee, Rob A. Rutenbar, L.Richard Carley
R4,565 Discovery Miles 45 650 Ships in 10 - 15 working days

Practical Synthesis of High-Performance Analog Circuits presents a technique for automating the design of analog circuits. Market competition and the astounding pace of technological innovation exert tremendous pressure on circuit design engineers to turn ideas into products quickly and get them to market. In digital Application Specific Integrated Circuit (ASIC) design, computer aided design (CAD) tools have substantially eased this pressure by automating many of the laborious steps in the design process, thereby allowing the designer to maximise his design expertise. But the world is not solely digital. Cellular telephones, magnetic disk drives, neural networks and speech recognition systems are a few of the recent technological innovations that rely on a core of analog circuitry and exploit the density and performance of mixed analog/digital ASICs. To maximize profit, these mixed-signal ASICs must also make it to market as quickly as possible. However, although the engineer working on the digital portion of the ASIC can rely on sophisticated CAD tools to automate much of the design process, there is little help for the engineer working on the analog portion of the chip. With the exception of simulators to verify the circuit design when it is complete, there are almost no general purpose CAD tools that an analog design engineer can take advantage of to automate the analog design flow and reduce his time to market. Practical Synthesis of High-Performance Analog Circuits presents a new variation-tolerant analog synthesis strategy that is a significant step towards ending the wait for a practical analog synthesis tool. A new synthesis strategy is presented that can fully automate the path from a circuit topology and performance specifications to a sized variation-tolerant circuit schematic. This strategy relies on asymptotic waveform evaluation to predict circuit performance and simulated annealing to solve a novel non-linear infinite programming optimization formulation of the circuit synthesis problem via a sequence of smaller optimization problems. Practical Synthesis of High-Performance Analog Circuits will be of interest to analog circuit designers, CAD EDA industry professionals, academics and students.

Analog Device-Level Layout Automation (Paperback, Softcover reprint of the original 1st ed. 1994): John M. Cohn, David J.... Analog Device-Level Layout Automation (Paperback, Softcover reprint of the original 1st ed. 1994)
John M. Cohn, David J. Garrod, Rob A. Rutenbar, Rick Carley
R4,561 Discovery Miles 45 610 Ships in 10 - 15 working days

This book presents a detailed summary of research on automatic layout of device-level analog circuits that was undertaken in the late 1980s and early 1990s at Carnegie Mellon University. We focus on the work behind the creation of the tools called KOAN and ANAGRAM II, which form part of the core of the CMU ACACIA analog CAD system. KOAN is a device placer for custom analog cells; ANANGRAM II a detailed area router for these analog cells. We strive to present the motivations behind the architecture of these tools, including detailed discussion of the subtle technology and circuit concerns that must be addressed in any successful analog or mixed-signal layout tool. Our approach in organizing the chapters of the book has been to present our algo rithms as a series of responses to these very real and very difficult analog layout problems. Finally, we present numerous examples of results generated by our algorithms. This research was supported in part by the Semiconductor Research Corpora tion, by the National Science Foundation, by Harris Semiconductor, and by the International Business Machines Corporation Resident Study Program. Finally, just for the record: John Cohn was the designer of the KOAN placer; David Garrod was the designer of the ANAGRAM II router (and its predeces sor, ANAGRAM I). This book was architected by all four authors, edited by John Cohn and Rob Rutenbar, and produced in finished form by John Cohn.

Novel Algorithms for Fast Statistical Analysis of Scaled Circuits (Paperback, 2009 ed.): Amith Singhee, Rob A. Rutenbar Novel Algorithms for Fast Statistical Analysis of Scaled Circuits (Paperback, 2009 ed.)
Amith Singhee, Rob A. Rutenbar
R2,978 Discovery Miles 29 780 Ships in 10 - 15 working days

As VLSI technology moves to the nanometer scale for transistor feature sizes, the impact of manufacturing imperfections result in large variations in the circuit performance. Traditional CAD tools are not well-equipped to handle this scenario, since they do not model this statistical nature of the circuit parameters and performances, or if they do, the existing techniques tend to be over-simplified or intractably slow. Novel Algorithms for Fast Statistical Analysis of Scaled Circuits draws upon ideas for attacking parallel problems in other technical fields, such as computational finance, machine learning and actuarial risk, and synthesizes them with innovative attacks for the problem domain of integrated circuits. The result is a set of novel solutions to problems of efficient statistical analysis of circuits in the nanometer regime.

Synthesis of Power Distribution to Manage Signal Integrity in Mixed-Signal ICs (Paperback, Softcover reprint of the original... Synthesis of Power Distribution to Manage Signal Integrity in Mixed-Signal ICs (Paperback, Softcover reprint of the original 1st ed. 1996)
Balsha R. Stanisic, Rob A. Rutenbar, L.Richard Carley
R2,985 Discovery Miles 29 850 Ships in 10 - 15 working days

In the early days of VLSI, the design of the power distribution for an integrated cir cuit was rather simple. Power distribution --the design of the geometric topology for the network of wires that connect the various power supplies, the widths of the indi vidual segments for each of these wires, the number and location of the power I/O pins around the periphery of the chip --was simple because the chips were simpler. Few available wiring layers forced floorplans that allowed simple, planar (non-over lapping) power networks. Lower speeds and circuit density made the choice of the wire widths easier: we made them just fat enough to avoid resistive voltage drops due to switching currents in the supply network. And we just didn't need enormous num bers of power and ground pins on the package for the chips to work. It's not so simple any more. Increased integration has forced us to focus on reliability concerns such as metal elec tromigration, which affects wire sizing decisions in the power network. Extra metal layers have allowed more flexibility in the topological layout of the power networks."

Automatic Programming Applied to VLSI CAD Software: A Case Study (Paperback, Softcover reprint of the original 1st ed. 1990):... Automatic Programming Applied to VLSI CAD Software: A Case Study (Paperback, Softcover reprint of the original 1st ed. 1990)
Dorothy E Setliff, Rob A. Rutenbar
R4,546 Discovery Miles 45 460 Ships in 10 - 15 working days

This book, and the research it describes, resulted from a simple observation we made sometime in 1986. Put simply, we noticed that many VLSI design tools looked "alike." That is, at least at the overall software architecture level, the algorithms and data structures required to solve problem X looked much like those required to solve problem X'. Unfortunately, this resemblance is often of little help in actually writing the software for problem X' given the software for problem X. In the VLSI CAD world, technology changes rapidly enough that design software must continually strive to keep up. And of course, VLSI design software, and engineering design software in general, is often exquisitely sensitive to some aspects of the domain (technology) in which it operates. Modest changes in functionality have an unfortunate tendency to require substantial (and time-consuming) internal software modifications. Now, observing that large engineering software systems are technology dependent is not particularly clever. However, we believe that our approach to xiv Preface dealing with this problem took an interesting new direction. We chose to investigate the extent to which automatic programming ideas cold be used to synthesize such software systems from high-level specifications. This book is one of the results of that effort."

Extreme Statistics in Nanoscale Memory Design (Hardcover, 2010 ed.): Amith Singhee, Rob A. Rutenbar Extreme Statistics in Nanoscale Memory Design (Hardcover, 2010 ed.)
Amith Singhee, Rob A. Rutenbar
R4,713 Discovery Miles 47 130 Ships in 10 - 15 working days

Knowledge exists: you only have to ?nd it VLSI design has come to an important in?ection point with the appearance of large manufacturing variations as semiconductor technology has moved to 45 nm feature sizes and below. If we ignore the random variations in the manufacturing process, simulation-based design essentially becomes useless, since its predictions will be far from the reality of manufactured ICs. On the other hand, using design margins based on some traditional notion of worst-case scenarios can force us to sacri?ce too much in terms of power consumption or manufacturing cost, to the extent of making the design goals even infeasible. We absolutely need to explicitly account for the statistics of this random variability, to have design margins that are accurate so that we can ?nd the optimum balance between yield loss and design cost. This discontinuity in design processes has led many researchers to develop effective methods of statistical design, where the designer can simulate not just the behavior of the nominal design, but the expected statistics of the behavior in manufactured ICs. Memory circuits tend to be the hardest hit by the problem of these random variations because of their high replication count on any single chip, which demands a very high statistical quality from the product. Requirements of 5-6s (0.

Novel Algorithms for Fast Statistical Analysis of Scaled Circuits (Hardcover, 2009 ed.): Amith Singhee, Rob A. Rutenbar Novel Algorithms for Fast Statistical Analysis of Scaled Circuits (Hardcover, 2009 ed.)
Amith Singhee, Rob A. Rutenbar
R3,130 Discovery Miles 31 300 Ships in 10 - 15 working days

As VLSI technology moves to the nanometer scale for transistor feature sizes, the impact of manufacturing imperfections result in large variations in the circuit performance. Traditional CAD tools are not well-equipped to handle this scenario, since they do not model this statistical nature of the circuit parameters and performances, or if they do, the existing techniques tend to be over-simplified or intractably slow. Novel Algorithms for Fast Statistical Analysis of Scaled Circuits draws upon ideas for attacking parallel problems in other technical fields, such as computational finance, machine learning and actuarial risk, and synthesizes them with innovative attacks for the problem domain of integrated circuits. The result is a set of novel solutions to problems of efficient statistical analysis of circuits in the nanometer regime.

Direct Transistor-Level Layout for Digital Blocks (Hardcover, 2004 ed.): Prakash Gopalakrishnan, Rob A. Rutenbar Direct Transistor-Level Layout for Digital Blocks (Hardcover, 2004 ed.)
Prakash Gopalakrishnan, Rob A. Rutenbar
R3,084 Discovery Miles 30 840 Ships in 10 - 15 working days

Cell-based design methodologies have dominated layout generation of digital circuits. Unfortunately, the growing demands for transparent process portability, increased performance, and low-level device sizing for timing/power are poorly handled in a fixed cell library.
Direct Transistor-Level Layout For Digital Blocks proposes a direct transistor-level layout approach for small blocks of custom digital logic as an alternative that better accommodates demands for device-level flexibility. This approach captures essential shape-level optimizations, yet scales easily to netlists with thousands of devices, and incorporates timing optimization during layout. The key idea is early identification of essential diffusion-merged MOS device groups, and their preservation in an uncommitted geometric form until the very end of detailed placement. Roughly speaking, essential groups are extracted early from the transistor-level netlist, placed globally, optimized locally, and then finally committed each to a specific shape-level form while concurrently optimizing for both density and routability.
The essential flaw in prior efforts is an over-reliance on geometric assumptions from large-scale cell-based layout algorithms. Individual transistors may seem simple, but they do not pack as gates do. Algorithms that ignore these shape-level issues suffer the consequences when thousands of devices are poorly packed. The approach described in this book can pack devices much more densely than a typical cell-based layout.
Direct Transistor-Level Layout For Digital Blocks is a comprehensive reference work on device-level layout optimization, which will be valuable to CAD tool and circuit designers.

Practical Synthesis of High-Performance Analog Circuits (Hardcover, 1998 ed.): Emil S. Ochotta, Tamal Mukherjee, Rob A.... Practical Synthesis of High-Performance Analog Circuits (Hardcover, 1998 ed.)
Emil S. Ochotta, Tamal Mukherjee, Rob A. Rutenbar, L.Richard Carley
R4,753 Discovery Miles 47 530 Ships in 10 - 15 working days

Practical Synthesis of High-Performance Analog Circuits presents a technique for automating the design of analog circuits. Market competition and the astounding pace of technological innovation exert tremendous pressure on circuit design engineers to turn ideas into products quickly and get them to market. In digital Application Specific Integrated Circuit (ASIC) design, computer aided design (CAD) tools have substantially eased this pressure by automating many of the laborious steps in the design process, thereby allowing the designer to maximise his design expertise. But the world is not solely digital. Cellular telephones, magnetic disk drives, neural networks and speech recognition systems are a few of the recent technological innovations that rely on a core of analog circuitry and exploit the density and performance of mixed analog/digital ASICs. To maximize profit, these mixed-signal ASICs must also make it to market as quickly as possible. However, although the engineer working on the digital portion of the ASIC can rely on sophisticated CAD tools to automate much of the design process, there is little help for the engineer working on the analog portion of the chip. With the exception of simulators to verify the circuit design when it is complete, there are almost no general purpose CAD tools that an analog design engineer can take advantage of to automate the analog design flow and reduce his time to market. Practical Synthesis of High-Performance Analog Circuits presents a new variation-tolerant analog synthesis strategy that is a significant step towards ending the wait for a practical analog synthesis tool. A new synthesis strategy is presented that can fully automate the path from a circuit topology and performance specifications to a sized variation-tolerant circuit schematic. This strategy relies on asymptotic waveform evaluation to predict circuit performance and simulated annealing to solve a novel non-linear infinite programming optimization formulation of the circuit synthesis problem via a sequence of smaller optimization problems. Practical Synthesis of High-Performance Analog Circuits will be of interest to analog circuit designers, CAD/EDA industry professionals, academics and students.

Synthesis of Power Distribution to Manage Signal Integrity in Mixed-Signal ICs (Hardcover, 1996 ed.): Balsha R. Stanisic, Rob... Synthesis of Power Distribution to Manage Signal Integrity in Mixed-Signal ICs (Hardcover, 1996 ed.)
Balsha R. Stanisic, Rob A. Rutenbar, L.Richard Carley
R3,145 Discovery Miles 31 450 Ships in 10 - 15 working days

The move to higher levels of integration has increased the fraction of application-specific integrated circuit (ASIC) designs containing both analog and digital circuits. While the die area for the analog portion of these chips is modest, the design time is often significant. This has motivated the development of automated analog physical design tools for cell-level place-and-route and system-level signal-integrity-routing. To date, there is no tool that has specifically addressed the critical design task of synthesizing the power distribution for the analog portion of an analog or mixed-signal ASIC. Synthesis of Power Distribution to Manage Signal Integrity in Mixed-Signal ICs describes algorithms for analog power distribution synthesis and demonstrates their effectiveness. Existing digital power bus synthesis algorithms have failed to address critical concerns for analog circuitry, thus yielding unacceptable results. These tools synthesize only the bus component of power distribution networks and only consider simplified DC aspects of macros and busses. Readers of the companion book in this series, Simulation Techniques and Solutions for Mixed-Signal Coupling in Integrated Circuits (Kluwer Academic Publishers), already recognize the inadequacy of this simplified view of the noise and power distribution problem in mixed-signal integrated circuits. Synthesis of Power Distribution to Manage Signal Integrity in Mixed-Signal ICs addresses power distribution synthesis for mixed-signal integrated circuits. Several key challenges in power distribution design are identified and automated methods to overcome them are described. This book presents a new formulation for the analog powerdistribution synthesis problem which synthesizes both the power busses power I/O cell assignment by evaluating DC, AC, and transient interaction between the macros, busses, chip substrate, and package. Furthermore, algorithms are introduced which simultaneously optimize power I/O cell assignment, macro cell substrate coupling, power bus topology selection and power bus sizing. Synthesis of Power Distribution to Manage Signal Integrity in Mixed-Signal ICs will be of interest to CAD designers and researchers specializing in physical design, modelling and circuit synthesis.

Analog Device-Level Layout Automation (Hardcover, 1994 ed.): John M. Cohn, David J. Garrod, Rob A. Rutenbar, Rick Carley Analog Device-Level Layout Automation (Hardcover, 1994 ed.)
John M. Cohn, David J. Garrod, Rob A. Rutenbar, Rick Carley
R4,747 Discovery Miles 47 470 Ships in 10 - 15 working days

This book presents a detailed summary of research on automatic layout of device-level analog circuits that was undertaken in the late 1980s and early 1990s at Carnegie Mellon University. We focus on the work behind the creation of the tools called KOAN and ANAGRAM II, which form part of the core of the CMU ACACIA analog CAD system. KOAN is a device placer for custom analog cells; ANANGRAM II a detailed area router for these analog cells. We strive to present the motivations behind the architecture of these tools, including detailed discussion of the subtle technology and circuit concerns that must be addressed in any successful analog or mixed-signal layout tool. Our approach in organizing the chapters of the book has been to present our algo rithms as a series of responses to these very real and very difficult analog layout problems. Finally, we present numerous examples of results generated by our algorithms. This research was supported in part by the Semiconductor Research Corpora tion, by the National Science Foundation, by Harris Semiconductor, and by the International Business Machines Corporation Resident Study Program. Finally, just for the record: John Cohn was the designer of the KOAN placer; David Garrod was the designer of the ANAGRAM II router (and its predeces sor, ANAGRAM I). This book was architected by all four authors, edited by John Cohn and Rob Rutenbar, and produced in finished form by John Cohn."

Automatic Programming Applied to VLSI CAD Software: A Case Study (Hardcover, 1990 ed.): Dorothy E Setliff, Rob A. Rutenbar Automatic Programming Applied to VLSI CAD Software: A Case Study (Hardcover, 1990 ed.)
Dorothy E Setliff, Rob A. Rutenbar
R4,715 Discovery Miles 47 150 Ships in 10 - 15 working days

This book, and the research it describes, resulted from a simple observation we made sometime in 1986. Put simply, we noticed that many VLSI design tools looked "alike." That is, at least at the overall software architecture level, the algorithms and data structures required to solve problem X looked much like those required to solve problem X'. Unfortunately, this resemblance is often of little help in actually writing the software for problem X' given the software for problem X. In the VLSI CAD world, technology changes rapidly enough that design software must continually strive to keep up. And of course, VLSI design software, and engineering design software in general, is often exquisitely sensitive to some aspects of the domain (technology) in which it operates. Modest changes in functionality have an unfortunate tendency to require substantial (and time-consuming) internal software modifications. Now, observing that large engineering software systems are technology dependent is not particularly clever. However, we believe that our approach to xiv Preface dealing with this problem took an interesting new direction. We chose to investigate the extent to which automatic programming ideas cold be used to synthesize such software systems from high-level specifications. This book is one of the results of that effort."

Free Delivery
Pinterest Twitter Facebook Google+
You may like...
Pulse Active Flat Cone (18cm)
R99 Discovery Miles 990
HP 330 Wireless Keyboard and Mouse Combo
R800 R450 Discovery Miles 4 500
An Introduction To Scholarship…
Cheryl Siewierski Paperback  (2)
R480 R99 Discovery Miles 990
Card Games - 52 Of The World's Best Card…
Sara Harper Hardcover  (1)
R360 R49 Discovery Miles 490
Microsoft Xbox Series Wireless…
R1,579 Discovery Miles 15 790
Fine Living 4 Layer Shelf (Matt Black…
R1,799 R1,099 Discovery Miles 10 990
Huntlea Koletto - Bolster Pet Bed (Kale…
R695 R279 Discovery Miles 2 790
Marltons Dog Blanket (100 x 100cm)
R99 R46 Discovery Miles 460
Crystal Aire Concentrate - Ocean Mist…
R199 Discovery Miles 1 990
Snookums Baby Honey Dummies (6 Months)
R75 R38 Discovery Miles 380

 

Partners