Companies must confront an increasingly competitive environment with lean, flexible and market oriented structures. Therefore companies organize themselves according to their business processes. These processes are more and more often designed, implemented and managed based on standard software, mostly ERP or SCM packages. This is the first book delivering a complete description of a business driven implementation of standard software packages, accelerated by the use of reference models and other information models. The use of those models ensures best quality results and speeds up the software implementation. The book discusses how companies can optimize business processes and realize strategic goals with the implementation of software like SAP R/3, Oracle, Baan or Peoplesoft. It also includes the post implementation activities. The book cites numerous case studies and outlines each step of a process oriented implementation, including the goals, procedures and necessary methods and tools.

This book describes algorithmic methods and parallelization techniques to design a parallel sparse direct solver which is specifically targeted at integrated circuit simulation problems. The authors describe a complete flow and detailed parallel algorithms of the sparse direct solver. They also show how to improve the performance by simple but effective numerical techniques. The sparse direct solver techniques described can be applied to any SPICE-like integrated circuit simulator and have been proven to be high-performance in actual circuit simulation. Readers will benefit from the state-of-the-art parallel integrated circuit simulation techniques described in this book, especially the latest parallel sparse matrix solution techniques.

Magnetic recording is expected to become core technology in a multi-billion dollar industry in the in the very near future. Some of the most critical discoveries regarding perpendicular write and playback heads and perpendicular media were made only during the last several years as a result of extensive and intensive research in both academia and industry in their fierce race to extend the superparamagnetic limit in the magnetic recording media. These discoveries appear to be critical for implementing perpendicular magnetic recording into an actual disk drive.

This book addresses all the open questions and issues which need to be resolved before perpendicular recording can finally be implemented successfully, and is the first monograph in many years to address this subject.

This book is intended for graduate students, young engineers and even senior and more experienced researchers in this field who need to acquire adequate knowledge of the physics of perpendicular magnetic recording in order to further develop the field of perpendicular recording.

Adiabatic logic is a potential successor for static CMOS circuit design when it comes to ultra-low-power energy consumption. Future development like the evolutionary shrinking of the minimum feature size as well as revolutionary novel transistor concepts will change the gate level savings gained by adiabatic logic. In addition, the impact of worsening degradation effects has to be considered in the design of adiabatic circuits. The impact of the technology trends on the figures of merit of adiabatic logic, energy saving potential and optimum operating frequency, are investigated, as well as degradation related issues. Adiabatic logic benefits from future devices, is not susceptible to Hot Carrier Injection, and shows less impact of Bias Temperature Instability than static CMOS circuits. Major interest also lies on the efficient generation of the applied power-clock signal. This oscillating power supply can be used to save energy in short idle times by disconnecting circuits. An efficient way to generate the power-clock is by means of the synchronous 2N2P LC oscillator, which is also robust with respect to pattern-induced capacitive variations. An easy to implement but powerful power-clock gating supplement is proposed by gating the synchronization signals. Diverse implementations to shut down the system are presented and rated for their applicability and other aspects like energy reduction capability and data retention. Advantageous usage of adiabatic logic requires compact and efficient arithmetic structures. A broad variety of adder structures and a Coordinate Rotation Digital Computer are compared and rated according to energy consumption and area usage, and the resulting energy saving potential against static CMOS proves the ultra-low-power capability of adiabatic logic. In the end, a new circuit topology has to compete with static CMOS also in productivity. On a 130nm test chip, a large scale test vehicle containing an FIR filter was implemented in adiabatic logic, utilizing a standard, library-based design flow, fabricated, measured and compared to simulations of a static CMOS counterpart, with measured saving factors compliant to the values gained by simulation. This leads to the conclusion that adiabatic logic is ready for productive design due to compatibility not only to CMOS technology, but also to electronic design automation (EDA) tools developed for static CMOS system design.

Integrated Research in Grid Computing presents a selection of the best papers presented at the CoreGRID Integration Workshop (CGIW2005), which took place on November 28-30, 2005 in Pisa, Italy. The aim of CoreGRID is to strengthen and advance scientific and technological excellence in the area of Grid and Peer-to-Peer technologies in order to overcome the current fragmentation and duplication of effort in this area. To achieve this objective, the workshop brought together a critical mass of well-established researchers (including 145 permanent researchers and 171 PhD students) from a number of institutions which have all constructed an ambitious joint program of activities. Priority in the workshop was given to work conducted in Tcollaboration between partners from different research institutions and to promising research proposals that could foster such collaboration in the future.

BiCMOS Technology and Applications, Second Edition provides a synthesis of available knowledge about the combination of bipolar and MOS transistors in a common integrated circuit - BiCMOS. In this new edition all chapters have been updated and completely new chapters on emerging topics have been added. In addition, BiCMOS Technology and Applications, Second Edition provides the reader with a knowledge of either CMOS or Bipolar technology/design a reference with which they can make educated decisions regarding the viability of BiCMOS in their own application. BiCMOS Technology and Applications, Second Edition is vital reading for practicing integrated circuit engineers as well as technical managers trying to evaluate business issues related to BiCMOS. As a textbook, this book is also appropriate at the graduate level for a special topics course in BiCMOS. A general knowledge in device physics, processing and circuit design is assumed. Given the division of the book, it lends itself well to a two-part course; one on technology and one on design. This will provide advanced students with a good understanding of tradeoffs between bipolar and MOS devices and circuits.

Logic Synthesis for Low Power VLSI Designs presents a systematic and comprehensive treatment of power modeling and optimization at the logic level. More precisely, this book provides a detailed presentation of methodologies, algorithms and CAD tools for power modeling, estimation and analysis, synthesis and optimization at the logic level. Logic Synthesis for Low Power VLSI Designs contains detailed descriptions of technology-dependent logic transformations and optimizations, technology decomposition and mapping, and post-mapping structural optimization techniques for low power. It also emphasizes the trade-off techniques for two-level and multi-level logic circuits that involve power dissipation and circuit speed, in the hope that the readers can better understand the issues and ways of achieving their power dissipation goal while meeting the timing constraints. Logic Synthesis for Low Power VLSI Designs is written for VLSI design engineers, CAD professionals, and students who have had a basic knowledge of CMOS digital design and logic synthesis.

This comprehensive textbook on the field programmable gate array (FPGA) covers its history, fundamental knowledge, architectures, device technologies, computer-aided design technologies, design tools, examples of application, and future trends. Programmable logic devices represented by FPGAs have been rapidly developed in recent years and have become key electronic devices used in most IT products. This book provides both complete introductions suitable for students and beginners, and high-level techniques useful for engineers and researchers in this field. Differently developed from usual integrated circuits, the FPGA has unique structures, design methodologies, and application techniques. Allowing programming by users, the device can dramatically reduce the rising cost of development in advanced semiconductor chips. The FPGA is now driving the most advanced semiconductor processes and is an all-in-one platform combining memory, CPUs, and various peripheral interfaces. This book introduces the FPGA from various aspects for readers of different levels. Novice learners can acquire a fundamental knowledge of the FPGA, including its history, from Chapter 1; the first half of Chapter 2; and Chapter 4. Professionals who are already familiar with the device will gain a deeper understanding of the structures and design methodologies from Chapters 3 and 5. Chapters 6-8 also provide advanced techniques and cutting-edge applications and trends useful for professionals. Although the first parts are mainly suitable for students, the advanced sections of the book will be valuable for professionals in acquiring an in-depth understanding of the FPGA to maximize the performance of the device.

This book discusses various aspects of cloud computing, in which trust and fault-tolerance models are included in a multilayered, cloud architecture. The authors present a variety of trust and fault models used in the cloud, comparing them based on their functionality and the layer in the cloud to which they respond. Various methods are discussed that can improve the performance of cloud architectures, in terms of trust and fault-tolerance, while providing better performance and quality of service to user. The discussion also includes new algorithms that overcome drawbacks of existing methods, using a performance matrix for each functionality. This book provide readers with an overview of cloud computing and how trust and faults in cloud datacenters affects the performance and quality of service assured to the users. Discusses fundamental issues related to trust and fault-tolerance in Cloud Computing; Describes trust and fault management techniques in multi layered cloud architecture to improve security, reliability and performance of the system; Includes methods to enhance power efficiency and network efficiency, using trust and fault based resource allocation.

This book encapsulates some work done in the DIRC project concerned with trust and responsibility in socio-technical systems. It brings together a range of disciplinary approaches - computer science, sociology and software engineering - to produce a socio-technical systems perspective on the issues surrounding trust in technology in complex settings. Computer systems can only bring about their purported benefits if functionality, users and usability are central to their design and deployment. Thus, technology can only be trusted in situ and in everyday use if these issues have been brought to bear on the process of technology design, implementation and use. The studies detailed in this book analyse the ways in which trust in technology is achieved and/or worked around in everyday situations in a range of settings - including hospitals, a steelworks, a public enquiry, the financial services sector and air traffic control.

The major thrust of this book is the realisation of an all optical computer. To that end it discusses optoelectronic devices and applications, transmission systems, integrated optoelectronic systems and, of course, all optical computers. The chapters on heterostructure light emitting devices' quantum well carrier transport optoelectronic devices' present the most recent advances in device physics, together with modern devices and their applications. The chapter on microcavity lasers' is essential to the discussion of present and future developments in solid-state laser physics and technology and puts into perspective the present state of research into and the technology of optoelectronic devices, within the context of their use in advanced systems. A significant part of the book deals with problems of propagation in quantum structures. soliton-based switching, gating and transmission systems' presents the basics of controlling the propagation of photons in solids and the use of this control in devices. The chapters on optoelectronic processing using smart pixels' and all optical computers' are preceded by introductory material in fundamentals of quantum structures for optoelectronic devices and systems' and linear and nonlinear absorption and reflection in quantum well structures'. It is clear that new architectures will be necessary if we are to fully utilise the potentiality of electrooptic devices in computing, but even current architectures and structures demonstrate the feasibility of the all optical computer: one that is possible today.

This book describes a circuit architecture for converting real analog signals into a digital format, suitable for digital signal processors. This architecture, referred to as multi-stage noise-shaping (MASH) Continuous-Time Sigma-Delta Modulators (CT- M), has the potential to provide better digital data quality and achieve better data rate conversion with lower power consumption. The authors not only cover MASH continuous-time sigma delta modulator fundamentals, but also provide a literature review that will allow students, professors, and professionals to catch up on the latest developments in related technology.

This book is a collection of the finalized versions of the papers presented at the third Eurographics Workshop on Graphics Hardware. The diversity of the contributions reflects the widening range of options for graphics hardware that can be exploited due to the constant evolution of VLSI and software technologies. The first part of the book deals with the algorithmic aspects of graphics systems in a hardware-oriented context. Topics are: VLSI design strategies, data distribution for ray-tracing, the advantages of point-driven image generation with respect to VLSI implementation, use of memory and ease of parallelization, ray-tracing, and image reconstruction. The second part is on specific hardware, on content addressable memories and voxel-based systems. The third part addresses parallel systems: massively parallel object-based architectures, two systems in which image generated by individual rendering systems are composited, a transputer-based parallel display processor.

In Part I, the impact of an integro-differential operator on parity logic engines (PLEs) as a tool for scientific modeling from scratch is presented. Part II outlines the fuzzy structural modeling approach for building new linear and nonlinear dynamical causal forecasting systems in terms of fuzzy cognitive maps (FCMs). Part III introduces the new type of autogenetic algorithms (AGAs) to the field of evolutionary computing. Altogether, these PLEs, FCMs, and AGAs may serve as conceptual and computational power tools.

This state-of-the-art monograph presents a coherent survey of a variety of methods and systems for formal hardware verification. It emphasizes the presentation of approaches that have matured into tools and systems usable for the actual verification of nontrivial circuits. All in all, the book is a representative and well-structured survey on the success and future potential of formal methods in proving the correctness of circuits. The various chapters describe the respective approaches supplying theoretical foundations as well as taking into account the application viewpoint. By applying all methods and systems presented to the same set of IFIP WG10.5 hardware verification examples, a valuable and fair analysis of the strenghts and weaknesses of the various approaches is given.

This book presents the cyber culture of micro, macro, cosmological, and virtual computing. The book shows how these work to formulate, explain, and predict the current processes and phenomena monitoring and controlling technology in the physical and virtual space.The authors posit a basic proposal to transform description of the function truth table and structure adjacency matrix to a qubit vector that focuses on memory-driven computing based on logic parallel operations performance. The authors offer a metric for the measurement of processes and phenomena in a cyberspace, and also the architecture of logic associative computing for decision-making and big data analysis.The book outlines an innovative theory and practice of design, test, simulation, and diagnosis of digital systems based on the use of a qubit coverage-vector to describe the functional components and structures. Authors provide a description of the technology for SoC HDL-model diagnosis, based on Test Assertion Blocks Activated Graph. Examples of cyber-physical systems for digital monitoring and cloud management of social objects and transport are proposed. A presented automaton model of cosmological computing explains the cyclical and harmonious evolution of matter-energy essence, and also a space-time form of the Universe.

As almost no other technology, embedded systems is an essential element of many innovations in automotive engineering. New functions and improvements of already existing functions, as well as the compliance with traffic regulations and customer requirements, have only become possible by the increasing use of electronic systems, especially in the fields of driving, safety, reliability, and functionality. Along with the functionalities that increase in number and have to cooperate, the complexity of the entire system will increase.

Synergy effects resulting from distributed application functionalities via several electronic control devies, exchanging information through the network brings about more complex system architectures with many different sub-networks, operating with different velocities and different protocol implementations.

To manage the increasing complexity of these systems, a deterministic behaviour of the control units and the communication network must be provided for, in particular when dealing with a distributed functionality.

From Specification to Embedded Systems Application documents recent approaches and results presented at the International Embedded Systems Symposium (IESS 2005), which was held in August 2005 in Manaus (Brazil) and sponsored by the International Federation for Information Processing (IFIP).

The topics which have been chosen for this working conference are very timely: design methodology, modeling, specification, software synthesis, power management, formal verification, testing, network, communication systems, distributed control systems, resource management and special aspects in system design.

The exploitationof parallel processing to improve computing speeds is being examined at virtually all levels of computer science, from the study of parallel algorithms to the development of microarchitectures which employ multiple functional units. The most visible aspect of this interest in parallel processing is the commercially available multiprocessor systems which have appeared in the past decade. Unfortunately, the lack of adequate software support for the development of scientific applications that will run efficiently on multiple processors has stunted the acceptance of such systems. One of the major impediments to achieving high parallel efficiency on many data-parallel scientific applications is communication overhead, which is exemplified by cache coherency traffic and global memory overhead of interprocessors with a logically shared address space and physically distributed memory. Such techniques can be used by scientific application designers seeking to optimize code for a particular high-performance computer. In addition, these techniques can be seen as a necesary step toward developing software to support efficient paralled programs. In multiprocessor sytems with physically distributed memory, reducing communication overhead involves both data partitioning and data placement. Adaptive Data Partitioning (ADP) reduces the execution time of parallel programs by minimizing interprocessor communication for iterative data-parallel loops with near-neighbor communication. Data placement schemes are presented that reduce communication overhead. Under the loop partition specified by ADP, global data is partitioned into classes for each processor, allowing each processor to cachecertain regions of the global data set. In addition, for many scientific applications, peak parallel efficiency is achieved only when machine-specific tradeoffs between load imbalance and communication are evaluated and utilized in choosing the data partition. The techniques in this book evaluate these tradeoffs to generate optimum cyclic partitions for data-parallel loops with either a linearly varying or uniform computational structure and either neighborhood or dimensional multicast communication patterns. This tradeoff is also treated within the CPR (Collective Partitioning and Remapping) algorithm, which partitions a collection of loops with various computational structures and communication patterns. Experiments that demonstrate the advantage of ADP, data placement, cyclic partitioning and CPR were conducted on the Encore Multimax and BBN TC2000 multiprocessors using the ADAPT system, a program partitioner which automatically restructures iterative data-parallel loops. This book serves as an excellent reference and may be used as the text for an advanced course on the subject.

There is an increasing demand for dynamic systems to become safer, more reliable and more economical in operation. This requirement extends beyond the normally accepted safety-critical systems e.g., nuclear reactors, aircraft and many chemical processes, to systems such as autonomous vehicles and some process control systems where the system availability is vital. The field of fault diagnosis for dynamic systems (including fault detection and isolation) has become an important topic of research. Many applications of qualitative and quantitative modelling, statistical processing and neural networks are now being planned and developed in complex engineering systems. Issues of Fault Diagnosis for Dynamic Systems has been prepared by experts in fault detection and isolation (FDI) and fault diagnosis with wide ranging experience.Subjects featured include: - Real plant application studies; - Non-linear observer methods; - Robust approaches to FDI; - The use of parity equations; - Statistical process monitoring; - Qualitative modelling for diagnosis; - Parameter estimation approaches to FDI; - Fault diagnosis for descriptor systems; - FDI in inertial navigation; - Stuctured approaches to FDI; - Change detection methods; - Bio-medical studies. Researchers and industrial experts will appreciate the combination of practical issues and mathematical theory with many examples. Control engineers will profit from the application studies.

It gives me immense pleasure to introduce this timely handbook to the research/- velopment communities in the ?eld of signal processing systems (SPS). This is the ?rst of its kind and represents state-of-the-arts coverage of research in this ?eld. The driving force behind information technologies (IT) hinges critically upon the major advances in both component integration and system integration. The major breakthrough for the former is undoubtedly the invention of IC in the 50's by Jack S. Kilby, the Nobel Prize Laureate in Physics 2000. In an integrated circuit, all components were made of the same semiconductor material. Beginning with the pocket calculator in 1964, there have been many increasingly complex applications followed. In fact, processing gates and memory storage on a chip have since then grown at an exponential rate, following Moore's Law. (Moore himself admitted that Moore's Law had turned out to be more accurate, longer lasting and deeper in impact than he ever imagined. ) With greater device integration, various signal processing systems have been realized for many killer IT applications. Further breakthroughs in computer sciences and Internet technologies have also catalyzed large-scale system integration. All these have led to today's IT revolution which has profound impacts on our lifestyle and overall prospect of humanity. (It is hard to imagine life today without mobiles or Internets ) The success of SPS requires a well-concerted integrated approach from mul- ple disciplines, such as device, design, and application.

The primary audience for this book are advanced undergraduate students and graduate students. Computer architecture, as it happened in other fields such as electronics, evolved from the small to the large, that is, it left the realm of low-level hardware constructs, and gained new dimensions, as distributed systems became the keyword for system implementation. As such, the system architect, today, assembles pieces of hardware that are at least as large as a computer or a network router or a LAN hub, and assigns pieces of software that are self-contained, such as client or server programs, Java applets or pro tocol modules, to those hardware components. The freedom she/he now has, is tremendously challenging. The problems alas, have increased too. What was before mastered and tested carefully before a fully-fledged mainframe or a closely-coupled computer cluster came out on the market, is today left to the responsibility of computer engineers and scientists invested in the role of system architects, who fulfil this role on behalf of software vendors and in tegrators, add-value system developers, R&D institutes, and final users. As system complexity, size and diversity grow, so increases the probability of in consistency, unreliability, non responsiveness and insecurity, not to mention the management overhead. What System Architects Need to Know The insight such an architect must have includes but goes well beyond, the functional properties of distributed systems."

Multiple processor systems are an important class of parallel systems. Over the years, several architectures have been proposed to build such systems to satisfy the requirements of high performance computing. These architectures span a wide variety of system types. At the low end of the spectrum, we can build a small, shared-memory parallel system with tens of processors. These systems typically use a bus to interconnect the processors and memory. Such systems, for example, are becoming commonplace in high-performance graph ics workstations. These systems are called uniform memory access (UMA) multiprocessors because they provide uniform access of memory to all pro cessors. These systems provide a single address space, which is preferred by programmers. This architecture, however, cannot be extended even to medium systems with hundreds of processors due to bus bandwidth limitations. To scale systems to medium range i. e., to hundreds of processors, non-bus interconnection networks have been proposed. These systems, for example, use a multistage dynamic interconnection network. Such systems also provide global, shared memory like the UMA systems. However, they introduce local and remote memories, which lead to non-uniform memory access (NUMA) architecture. Distributed-memory architecture is used for systems with thousands of pro cessors. These systems differ from the shared-memory architectures in that there is no globally accessible shared memory. Instead, they use message pass ing to facilitate communication among the processors. As a result, they do not provide single address space."

THE CONTEXT OF PARALLEL PROCESSING The field of digital computer architecture has grown explosively in the past two decades. Through a steady stream of experimental research, tool-building efforts, and theoretical studies, the design of an instruction-set architecture, once considered an art, has been transformed into one of the most quantitative branches of computer technology. At the same time, better understanding of various forms of concurrency, from standard pipelining to massive parallelism, and invention of architectural structures to support a reasonably efficient and user-friendly programming model for such systems, has allowed hardware performance to continue its exponential growth. This trend is expected to continue in the near future. This explosive growth, linked with the expectation that performance will continue its exponential rise with each new generation of hardware and that (in stark contrast to software) computer hardware will function correctly as soon as it comes off the assembly line, has its down side. It has led to unprecedented hardware complexity and almost intolerable dev- opment costs. The challenge facing current and future computer designers is to institute simplicity where we now have complexity; to use fundamental theories being developed in this area to gain performance and ease-of-use benefits from simpler circuits; to understand the interplay between technological capabilities and limitations, on the one hand, and design decisions based on user and application requirements on the other.

Developing correct and efficient software is far more complex for parallel and distributed systems than it is for sequential processors. Some of the reasons for this added complexity are: the lack of a universally acceptable parallel and distributed programming paradigm, the criticality of achieving high performance, and the difficulty of writing correct parallel and distributed programs. These factors collectively influence the current status of parallel and distributed software development tools efforts. Tools and Environments for Parallel and Distributed Systems addresses the above issues by describing working tools and environments, and gives a solid overview of some of the fundamental research being done worldwide. Topics covered in this collection are: mainstream program development tools, performance prediction tools and studies; debugging tools and research; and nontraditional tools. Audience: Suitable as a secondary text for graduate level courses in software engineering and parallel and distributed systems, and as a reference for researchers and practitioners in industry.