Grids are a crucial enabling technology for scientific and industrial development. Grid and Services Evolution, the 11th edited volume of the CoreGRID series, was based on The CoreGRID Middleware Workshop, held in Barcelona, Spain, June 5-6, 2008.

Grid and Services Evolution provides a bridge between the application community and the developers of middleware services, especially in terms of parallel computing. This edited volume brings together a critical mass of well-established researchers worldwide, from forty-two institutions active in the fields of distributed systems and middleware, programming models, algorithms, tools and environments.

Grid and Services Evolution is designed for a professional audience composed of researchers and practitioners within the Grid community industry. This volume is also suitable for advanced-level students in computer science.

In this volume organizational learning theory is used to analyse various practices of managing and facilitating knowledge sharing within companies. Experiences with three types of knowledge sharing, namely knowledge acquisition, knowledge reuse, and knowledge creation, at ten large companies are discussed and analyzed. This critical analysis leads to the identification of traps and obstacles when managing knowledge sharing, when supporting knowledge sharing with IT tools, and when organizations try to learn from knowledge sharing practices. The identification of these risks is followed by a discussion of how organizations can avoid them.

This work will be of interest to researchers and practitioners working in organization science and business administration. Also, consultants and organizations at large will find the book useful as it will provide them with insights into how other organizations manage and facilitate knowledge sharing and how potential failures can be prevented.

This book discusses the trade-offs involved in designing direct RF digitization receivers for the radio frequency and digital signal processing domains. A system-level framework is developed, quantifying the relevant impairments of the signal processing chain, through a comprehensive system-level analysis. Special focus is given to noise analysis (thermal noise, quantization noise, saturation noise, signal-dependent noise), broadband non-linear distortion analysis, including the impact of the sampling strategy (low-pass, band-pass), analysis of time-interleaved ADC channel mismatches, sampling clock purity and digital channel selection. The system-level framework described is applied to the design of a cable multi-channel RF direct digitization receiver. An optimum RF signal conditioning, and some algorithms (automatic gain control loop, RF front-end amplitude equalization control loop) are used to relax the requirements of a 2.7GHz 11-bit ADC.
A two-chip implementation is presented, using BiCMOS and 65nm CMOS processes, together with the block and system-level measurement results. Readers will benefit from the techniques presented, which are highly competitive, both in terms of cost and RF performance, while drastically reducing power consumption.
"

The most exciting development in parallel computer architecture is the convergence of traditionally disparate approaches on a common machine structure. This book explains the forces behind this convergence of shared-memory, message-passing, data parallel, and data-driven computing architectures. It then examines the design issues that are critical to all parallel architecture across the full range of modern design, covering data access, communication performance, coordination of cooperative work, and correct implementation of useful semantics. It not only describes the hardware and software techniques for addressing each of these issues but also explores how these techniques interact in the same system. Examining architecture from an application-driven perspective, it provides comprehensive discussions of parallel programming for high performance and of workload-driven evaluation, based on understanding hardware-software interactions.
* synthesizes a decade of research and development for practicing engineers, graduate students, and researchers in parallel computer architecture, system software, and applications development
* presents in-depth application case studies from computer graphics, computational science and engineering, and data mining to demonstrate sound quantitative evaluation of design trade-offs
* describes the process of programming for performance, including both the architecture-independent and architecture-dependent aspects, with examples and case-studies
* illustrates bus-based and network-based parallel systems with case studies of more than a dozen important commercial designs

This book provides graduate students and practitioners with knowledge of the CORBA standard and practical experience of implementing distributed systems with CORBA's Java mapping. With tested code examples that will run immediately!

Ferroelectric memories have changed in 10 short years from academic curiosities of the university research labs to commercial devices in large-scale production. This is the first text on ferroelectric memories that is not just an edited collection of papers by different authors. Intended for applied physicists, electrical engineers, materials scientists and ceramists, it includes ferroelectric fundamentals, especially for thin films, circuit diagrams and processsing chapters, but emphazises device physics. Breakdown mechanisms, switching kinetics and leakage current mechanisms have lengthly chapters devoted to them. The book will be welcomed by research scientists in industry and government laboratories and in universities. It also contains 76 problems for students, making it particularly useful as a textbook for fourth-year undergraduate or first-year graduate students.

The BeOS is the exciting new operating system designed natively for the Internet and digital media. Programmers are drawn to the BeOS by its many state-of-the-art features, including pervasive multithreading, a symmetric multiprocessing architecture, and an integrated multithreaded graphics system. The Be engineering team also built in many UNIX-like capabilities as part of a POSIX toolkit. Best of all, the BeOS runs on a variety of Intel architectures and PowerPC platforms and uses off-the-shelf hardware.

This book explores the BeOS from a POSIX programmer's point of view, providing a comprehensive and practical guide to porting UNIX and other POSIX-based software to the BeOS. BeOS: Porting UNIX Applications will help you move your favorite UNIX software to an environment designed from the ground up for high-performance applications.
* Supports BeOS Release 3
* Provides a step-by-step guide to the porting process from downloading the source code to installing the application
* Explains how to port off-the-shelf utilities like Emacs and Perl as well as your own programs and tools to the BeOS
* Offers a comprehensive POSIX reference for anyone who is porting or writing software for the BeOS
* Furnishes a simple catalog of tools and features available on the BeOS

The continous development of computer technology supported by the VLSI revolution stimulated the research in the field .of multiprocessors systems. The main motivation for the migration of design efforts from conventional architectures towards multiprocessor ones is the possibi I ity to obtain a significant processing power together with the improvement of price/performance, reliability and flexibility figures. Currently, such systems are moving from research laboratories to real field appl ications. Future technological advances and new generations of components are I ikely to further enhance this trend. This book is intended to provide basic concepts and design methodologies for engineers and researchers involved in the development of mul tiprocessor systems and/or of appl ications based on multiprocessor architectures. In addition the book can be a source of material for computer architecture courses at graduate level. A preliminary knowledge of computer architecture and logical design has been assumed in wri ting this book. Not all the problems related with the development of multiprocessor systems are addressed in th i s book. The covered range spans from the electrical and logical design problems, to architectural issues, to design methodologis for system software. Subj ects such as software development in a multiprocessor environment or loosely coupled multiprocessor systems are out of the scope of the book. Since the basic elements, processors and memories, are now available as standard integrated circuits, the key design problem is how to put them together in an efficient and reliable way."

This volume comprises a collection of twenty written versions of invited as well as contributed papers presented at the conference held from 20-24 May 1996 in Beijing, China. It covers many areas of logic and the foundations of mathematics, as well as computer science. Also included is an article by M. Yasugi on the Asian Logic Conference which first appeared in Japanese, to provide a glimpse into the history and development of the series.

This Handbook is the first volume of the International Handbook on Information Systems. It offers a comprehensive overview of architectures, languages, methods, and techniques for modelling and analysing information systems in organisations. The contributions are written by authoritative figures in this area. Numerous approaches are surveyed coming from computer science, information systems, and business administration among others. This volume brings together more than 30 contributions in order to provide a reference source for problem solvers in business, industry, and government, and which can be used by professional researchers and graduate students. In the new edition, all contributions have been revised completely. New papers have been added on XML and UML.

The core idea of this book is that object- oriented technology is a generic technology whose various technical aspects can be presented in a unified and consistent framework. This applies to both practical and formal aspects of object-oriented technology. Course tested in a variety of object-oriented courses, numerous examples, figures and exercises are presented in each chapter. The approach in this book is based on typed technologies, and the core notions fit mainstream object-oriented languages such as Java and C#. The book promotes object-oriented constraints (assertions), their specification and verification. Object-oriented constraints apply to specification and verification of object-oriented programs, specification of the object-oriented platform, more advanced concurrent models, database integrity constraints and object-oriented transactions, their specification and verification.

Parallel Numerical Computations with Applications contains selected edited papers presented at the 1998 Frontiers of Parallel Numerical Computations and Applications Workshop, along with invited papers from leading researchers around the world. These papers cover a broad spectrum of topics on parallel numerical computation with applications; such as advanced parallel numerical and computational optimization methods, novel parallel computing techniques, numerical fluid mechanics, and other applications related to material sciences, signal and image processing, semiconductor technology, and electronic circuits and systems design. This state-of-the-art volume will be an up-to-date resource for researchers in the areas of parallel and distributed computing.

This volume is the first diverse and comprehensive treatment of algorithms and architectures for the realization of neural network systems. It presents techniques and diverse methods in numerous areas of this broad subject. The book covers major neural network systems structures for achieving effective systems, and illustrates them with examples.
This volume includes Radial Basis Function networks, the Expand-and-Truncate Learning algorithm for the synthesis of Three-Layer Threshold Networks, weight initialization, fast and efficient variants of Hamming and Hopfield neural networks, discrete time synchronous multilevel neural systems with reduced VLSI demands, probabilistic design techniques, time-based techniques, techniques for reducing physical realization requirements, and applications to finite constraint problems.
A unique and comprehensive reference for a broad array of algorithms and architectures, this book will be of use to practitioners, researchers, and students in industrial, manufacturing, electrical, and mechanical engineering, as well as in computer science and engineering.
Key Features
* Radial Basis Function networks
* The Expand-and-Truncate Learning algorithm for the synthesis of Three-Layer Threshold Networks
* Weight initialization
* Fast and efficient variants of Hamming and Hopfield neural networks
* Discrete time synchronous multilevel neural systems with reduced VLSI demands
* Probabilistic design techniques
* Time-based techniques
* Techniques for reducing physical realization requirements
* Applications to finite constraint problems
* Practical realization methods for Hebbian type associative memory systems
*Parallel self-organizing hierarchical neural network systems
* Dynamics of networks of biological neurons for utilization in computational neuroscience
Practitioners, researchers, and students in industrial, manufacturing, electrical, and mechanical engineering, as well as in computer science and engineering, will find this volume a unique and comprehensive reference to a broad array of algorithms and architectures

This book introduces a novel design methodology which can significantly reduce the ASIP development effort through high degrees of design automation. The key elements of this new design methodology are a powerful application profiler and an automated instruction-set customization tool which considerably lighten the burden of mapping a target application to an ASIP architecture in the initial design stages. The book includes several design case studies with real life embedded applications to demonstrate how the methodology and the tools can be used in practice for accelerating the overall ASIP design process.

The kernel of any operating system is its most critical component, as the rest of the system depends on it. This book shows how the formal specification of kernels can be followed by a completely formal refinement process that leads to the extraction of executable code. This formal refinement process ensures that the code precisely meets the specification. The author documents the complete process, including proofs.

This book describes a comprehensive approach for synthesis and optimization of logic-in-memory computing hardware and architectures using memristive devices, which creates a firm foundation for practical applications. Readers will get familiar with a new generation of computer architectures that potentially can perform faster, as the necessity for communication between the processor and memory is surpassed. The discussion includes various synthesis methodologies and optimization algorithms targeting implementation cost metrics including latency and area overhead as well as the reliability issue caused by short memory lifetime. Presents a comprehensive synthesis flow for the emerging field of logic-in-memory computing; Describes automated compilation of programmable logic-in-memory computer architectures; Includes several effective optimization algorithm also applicable to classical logic synthesis; Investigates unbalanced write traffic in logic-in-memory architectures and describes wear leveling approaches to alleviate it.

Quantum Communication, Quantum Networks, and Quantum Sensing represents a self-contained introduction to quantum communication, quantum error-correction, quantum networks, and quantum sensing. It starts with basic concepts from classical detection theory, information theory, and channel coding fundamentals before continuing with basic principles of quantum mechanics including state vectors, operators, density operators, measurements, and dynamics of a quantum system. It continues with fundamental principles of quantum information processing, basic quantum gates, no-cloning and theorem on indistinguishability of arbitrary quantum states. The book then focuses on quantum information theory, quantum detection and Gaussian quantum information theories, and quantum key distribution (QKD). The book then covers quantum error correction codes (QECCs) before introducing quantum networks. The book concludes with quantum sensing and quantum radars, quantum machine learning and fault-tolerant quantum error correction concepts.

Recent developments in computer science clearly show the need for a better theoretical foundation for some central issues. Methods and results from mathematical logic, in particular proof theory and model theory, are of great help here and will be used much more in future than previously. This book provides an excellent introduction to the interplay of mathematical logic and computer science. It contains extensively reworked versions of the lectures given at the 1997 Marktoberdorf Summer School by leading researchers in the field.
Topics covered include: proof theory and specification of computation (J.-Y. Girard, D. Miller), complexity of proofs and programs (S. R. Buss, S. S. Wainer), computational content of proofs (H. Schwichtenberg), constructive type theory (P. Aczel, H. Barendregt, R. L. Constable), computational mathematics, (U. Martin), rewriting logic (J. Meseguer), and game semantics (S. Abramski).

At the beginning of the 1990s research started in how to combine soft comput ing with reconfigurable hardware in a quite unique way. One of the methods that was developed has been called evolvable hardware. Thanks to evolution ary algorithms researchers have started to evolve electronic circuits routinely. A number of interesting circuits - with features unreachable by means of con ventional techniques - have been developed. Evolvable hardware is quite pop ular right now; more than fifty research groups are spread out over the world. Evolvable hardware has become a part of the curriculum at some universi ties. Evolvable hardware is being commercialized and there are specialized conferences devoted to evolvable hardware. On the other hand, surprisingly, we can feel the lack of a theoretical background and consistent design methodology in the area. Furthermore, it is quite difficult to implement really innovative and practically successful evolvable systems using contemporary digital reconfigurable technology."

A Flash memory is a Non Volatile Memory (NVM) whose "unit cells" are fabricated in CMOS technology and programmed and erased electrically. In 1971, Frohman-Bentchkowsky developed a folating polysilicon gate tran sistor [1, 2], in which hot electrons were injected in the floating gate and removed by either Ultra-Violet (UV) internal photoemission or by Fowler Nordheim tunneling. This is the "unit cell" of EPROM (Electrically Pro grammable Read Only Memory), which, consisting of a single transistor, can be very densely integrated. EPROM memories are electrically programmed and erased by UV exposure for 20-30 mins. In the late 1970s, there have been many efforts to develop an electrically erasable EPROM, which resulted in EEPROMs (Electrically Erasable Programmable ROMs). EEPROMs use hot electron tunneling for program and Fowler-Nordheim tunneling for erase. The EEPROM cell consists of two transistors and a tunnel oxide, thus it is two or three times the size of an EPROM. Successively, the combination of hot carrier programming and tunnel erase was rediscovered to achieve a single transistor EEPROM, called Flash EEPROM. The first cell based on this concept has been presented in 1979 [3]; the first commercial product, a 256K memory chip, has been presented by Toshiba in 1984 [4]. The market did not take off until this technology was proven to be reliable and manufacturable [5].

This book brings together concepts and approaches from the fields of photogrammetry and computer vision. In particular, it examines techniques relating to quantitative image analysis, such as orientation, camera modelling, system calibration, self-calibration and error handling. The chapters have been contributed by experts in the relevant fields, and there are examples from automated inspection systems and other real-world cases. The book provides study material for students, researchers, developers and practitioners.

This volume contains selected papers from the 10th Interdisciplinary Workshop in Informatics and Psychology which had as its theme Cognitive Aspects in Visual Languages and Interfaces. Visual languages in general, visual programming languages in particular, and graphical or visual user interfaces are increasingly regarded as important improvements for the interaction between people and artifacts. Visual and graphical user interfaces have already a history of a number of years in terms of research and development. The focus on visual languages and visual programming languages, however, is more recent. The development of graphical user interfaces was accompanied and reinforced by psychological research but visual languages are still mainly inventions of designers and not designed on the basis of principles derived also from knowledge of psychology or other behavioral sciences.

The presentations and discussions at the workshop showed increasing interest in paradigms of visual languages and their psychological foundation. Visual languages and interfaces must be seen as means to support and enhance represention, application and processing knowledge visually. The study of the cognitive aspects in visual languages and interfaces is thus an important part of Human-Computer Interaction as a discipline "concerned with the design, evaluation and implementation of interactive computer systems for human use and with the study of major phenomena surrounding them" (definition of HCI in the ACM SIGCHI Curricula for Human-Computer Interaction). This book will stimulate future research in the area of Human-Computer Interaction and Visual Languages.

This book grants the reader a comprehensive overview of the state-of-the-art in system-level memory management (data transfer and storage) related issues for complex data-dominated real-time signal and data processing applications. The authors introduce their own system-level data transfer and storage exploration methodology for data-dominated video applications. This methodology tackles the power and area reduction cost components in the architecture for this target domain, namely the system-level busses and the background memories. For the most critical tasks in the methodology, prototype tools have been developed to reduce the design time. The approach is also very heavily application-driven which is illustrated by several realistic demonstrators, partly used as red-thread examples in the book. The quite general applicability and effectiveness has been substantiated for several industrial data-dominated applications, including H.263 video conferencing decoding and medical computer tomography (CT) back projection. To the researcher the book will serve as an excellent reference source, both for the overall description of the methodology and for the detailed descriptions of the system-level methodologies and synthesis techniques and algorithms. To the design engineers and CAD managers it offers an invaluable insight into the anticipated evolution of commercially available design tools as well as allowing them to utilize the book's concepts in their own research and development.

This book provides a comprehensive overview of the state-of-the-art, data flow-based techniques for the analysis, modeling and mapping technologies of concurrent applications on multi-processors. The authors present a flow for designing embedded hard/firm real-time multiprocessor streaming applications, based on data flow formalisms, with a particular focus on wireless modem applications. Architectures are described for the design tools and run-time scheduling and resource management of such a platform.
"