Distributed and Parallel Systems: From Cluster to Grid Computing, is an edited volume based on DAPSYS 2006, the 6th Austrian-Hungarian Workshop on Distributed and Parallel Systems, which is dedicated to all aspects of distributed and parallel computing. The workshop was held in conjunction with the 2nd Austrian Grid Symposium in Innsbruck, Austria in September 2006. This book is designed for a professional audience composed of practitioners and researchers in industry. It is also suitable for advanced-level students in computer science.

Networks on Chip presents a variety of topics, problems and approaches with the common theme to systematically organize the on-chip communication in the form of a regular, shared communication network on chip, an NoC for short.

As the number of processor cores and IP blocks integrated on a single chip is steadily growing, a systematic approach to design the communication infrastructure becomes necessary. Different variants of packed switched on-chip networks have been proposed by several groups during the past two years. This book summarizes the state of the art of these efforts and discusses the major issues from the physical integration to architecture to operating systems and application interfaces. It also provides a guideline and vision about the direction this field is moving to. Moreover, the book outlines the consequences of adopting design platforms based on packet switched network. The consequences may in fact be far reaching because many of the topics of distributed systems, distributed real-time systems, fault tolerant systems, parallel computer architecture, parallel programming as well as traditional system-on-chip issues will appear relevant but within the constraints of a single chip VLSI implementation.

The book is organized in three parts. The first deals with system design and methodology issues. The second presents problems and solutions concerning the hardware and the basic communication infrastructure. Finally, the third part covers operating system, embedded software and application. However, communication from the physical to the application level is a central theme throughout the book.

The book serves as an excellent reference source and may be used as a text for advanced courses on the subject.

Making Grids Work includes selected articles from the CoreGRID Workshop on Grid Programming Models, Grid and P2P Systems Architecture, Grid Systems, Tools and Environments held at the Institute of Computer Science, Foundation for Research and Technology - Hellas in Crete, Greece, June 2007. This workshop brought together representatives of the academic and industrial communities performing Grid research in Europe. Organized within the context of the CoreGRID Network of Excellence, this workshop provided a forum for the presentation and exchange of views on the latest developments in Grid Technology research. This volume is the 7th in the series of CoreGRID books. Making Grids Work is designed for a professional audience, composed of researchers and practitioners in industry. This volume is also suitable for graduate-level students in computer science.

This book constitutes the thoroughly refereed and revised proceedings of the 9th International Workshop on Computational Logic for Multi-Agent Systems, CLIMA IX, held in Dresden, Germany, in September 2008 and co-located with the 11th European Conference on Logics in Artificial Intelligence, JELIA 2008.

The 8 full papers, presented together with two invited papers, were carefull selected from 18 submissions and passed through two rounds of reviewing and revision. Topics addressed in the regular papers include the use of automata-based techniques for verifying agents' conformance with protocols, and an approach based on the C+ action description language to provide formal specifications of social processes such as those used in business processes and social networks. Other topics include casting reasoning as planning and thus providing an analysis of reasoning with resource bounds, a discussion of the formal properties of Computational Tree Logic (CTL) extended with knowledge operators, and the use of argumentation in multi-agent negotiation. The invited contributions discuss complexity results for model-checking temporal and strategic properties of multi-agent systems, and the challenges in design and development of programming languages for multi-agent systems.

Process-Driven SOA: Patterns for Aligning Business and IT supplies detailed guidance on how to design and build software architectures that follow the principles of business-IT alignment. It illustrates the design process using proven patterns that address complex business/technical scenarios, where integrated concepts of service-oriented architecture (SOA), Business Process Management (BPM), and Event-Driven Architecture (EDA) are required. The book demonstrates that SOA is not limited to technical issues but instead, is a holistic challenge where aspects of SOA, EDA, and BPM must be addressed together. An ideal guide for SOA solution architects, designers, developers, managers, and students about to enter the field, the book: Provides an accessible introduction to basic and more advanced concepts in process-driven SOA Illustrates how to manage the complexities of business aligned IT architectures with detailed examples and industry cases Outlines a step-by-step design process using proven patterns to address complex business/ technical scenarios Integrates SOA, BPM, and EDA into practical patterns promoting SOA 2.0 Describing how to synchronize parallel enterprise processes, the authors explain how to cope with the architectural and design decisions you are likely to encounter when designing and implementing process-driven SOA systems. The decisions are described in the form of software patterns to provide you with a practical guideline for addressing key problems using time-tested solutions.

Going beyond isolated research ideas and design experiences, Designing Network On-Chip Architectures in the Nanoscale Era covers the foundations and design methods of network on-chip (NoC) technology. The contributors draw on their own lessons learned to provide strong practical guidance on various design issues. Exploring the design process of the network, the first part of the book focuses on basic aspects of switch architecture and design, topology selection, and routing implementation. In the second part, contributors discuss their experiences in the industry, offering a roadmap to recent products. They describe Tilera's TILE family of multicore processors, novel Intel products and research prototypes, and the TRIPS operand network (OPN). The last part reveals state-of-the-art solutions to hardware-related issues and explains how to efficiently implement the programming model at the network interface. In the appendix, the microarchitectural details of two switch architectures targeting multiprocessor system-on-chips (MPSoCs) and chip multiprocessors (CMPs) can be used as an experimental platform for running tests. A stepping stone to the evolution of future chip architectures, this volume provides a how-to guide for designers of current NoCs as well as designers involved with 2015 computing platforms. It cohesively brings together fundamental design issues, alternative design paradigms and techniques, and the main design tradeoffs-consistently focusing on topics most pertinent to real-world NoC designers.

Heterogeneous Computing Architectures: Challenges and Vision provides an updated vision of the state-of-the-art of heterogeneous computing systems, covering all the aspects related to their design: from the architecture and programming models to hardware/software integration and orchestration to real-time and security requirements. The transitions from multicore processors, GPU computing, and Cloud computing are not separate trends, but aspects of a single trend-mainstream; computers from desktop to smartphones are being permanently transformed into heterogeneous supercomputer clusters. The reader will get an organic perspective of modern heterogeneous systems and their future evolution.

System architects and engineers in fields such as storage networking, desktop computing, electrical power distribution, and telecommunications need a common and flexible way of managing heterogeneous devices and services. Web-Based Enterprise Management (WBEM) and its Component Information Model (CIM) provide the architecture, language, interfaces, and common models for the management of storage, computing, and telecommunication applications. Now there is a practical guide for those who design or implement the emerging WBEM systems or produce a CIM model of a device or service. A Practical Approach to WBEM/CIM Management describes in detail WBEM/CIM architecture and explores the standard models developed by the Distributed Management Task Force (DMTF). It explores the interfaces with which your WBEM/CIM code will have to work, and offers examples of applicable models and related code. This book introduces the components of WBEM architecture, defines models within CIM, and illustrates communication between the WBEM client and server. It also investigates transitioning from SNMP or proprietary systems to WBEM/CIM. Realizing that the field is undergoing a period of massive growth and change, the author focuses primarily on the areas which have been standardized and which differ little between implementations. He does, however, provide coding examples using the openPegasus implementation, demonstrating concepts common to other C++ and Java-based implementations.

Bring agility, cost savings, and a competitive edge to your business by migrating your IT infrastructure to AWS. With this practical book, executive and senior leadership and engineering and IT managers will examine the advantages, disadvantages, and common pitfalls when moving your company's operations to the cloud. Author Jeff Armstrong brings years of practical hands-on experience helping dozens of enterprises make this corporate change. You'll explore real-world examples from many organizations that have made-or attempted to make-this wide-ranging transition. Once you read this guide, you'll be better prepared to evaluate your migration objectively before, during, and after the process in order to ensure success. Learn the benefits and drawbacks of migrating to AWS, including the risks to your business and technology Begin the process by discovering the applications and servers in your environment Examine the value of AWS migration when building your business case Address your operational readiness before you migrate Define your AWS account structure and cloud governance controls Create your migration plan in waves of servers and applications Refactor applications that will benefit from using more cloud native resources

Using a unique pedagogical approach, this text introduces mathematical logic by guiding students in implementing the underlying logical concepts and mathematical proofs via Python programming. This approach, tailored to the unique intuitions and strengths of the ever-growing population of programming-savvy students, brings mathematical logic into the comfort zone of these students and provides clarity that can only be achieved by a deep hands-on understanding and the satisfaction of having created working code. While the approach is unique, the text follows the same set of topics typically covered in a one-semester undergraduate course, including propositional logic and first-order predicate logic, culminating in a proof of Goedel's completeness theorem. A sneak peek to Goedel's incompleteness theorem is also provided. The textbook is accompanied by an extensive collection of programming tasks, code skeletons, and unit tests. Familiarity with proofs and basic proficiency in Python is assumed.

Going beyond isolated research ideas and design experiences, Designing Network On-Chip Architectures in the Nanoscale Era covers the foundations and design methods of network on-chip (NoC) technology. The contributors draw on their own lessons learned to provide strong practical guidance on various design issues. Exploring the design process of the network, the first part of the book focuses on basic aspects of switch architecture and design, topology selection, and routing implementation. In the second part, contributors discuss their experiences in the industry, offering a roadmap to recent products. They describe Tilera's TILE family of multicore processors, novel Intel products and research prototypes, and the TRIPS operand network (OPN). The last part reveals state-of-the-art solutions to hardware-related issues and explains how to efficiently implement the programming model at the network interface. In the appendix, the microarchitectural details of two switch architectures targeting multiprocessor system-on-chips (MPSoCs) and chip multiprocessors (CMPs) can be used as an experimental platform for running tests. A stepping stone to the evolution of future chip architectures, this volume provides a how-to guide for designers of current NoCs as well as designers involved with 2015 computing platforms. It cohesively brings together fundamental design issues, alternative design paradigms and techniques, and the main design tradeoffs-consistently focusing on topics most pertinent to real-world NoC designers.

Safety-critical systems, by definition those systems whose failure can cause catastrophic results for people, the environment, and the economy, are becoming increasingly complex both in their functionality and their interactions with the environment. Unfortunately, safety assessments are still largely done manually, a time-consuming and error-prone process. The growing complexity of these systems requires an increase in the skill and efficacy of safety engineers and encourages the adoption of formal and standardized techniques.

An introduction to the area of design and verification of safety-critical systems, Design and Safety Assessment of Critical Systems focuses on safety assessment using formal methods. Beginning with an introduction to the fundamental concepts of safety and reliability, it illustrates the pivotal issues of design, development, and safety assessment of critical systems.

The core of the book covers traditional notations, techniques, and procedures, including Fault Tree Analysis, FMECA, HAZOP, and Event Tree Analysis, and explains in detail how formal methods can be used to realize such procedures. It looks at the development process of safety-critical systems, and highlights influential management and organizational aspects. Finally, it describes verification and validation techniques and new trends in formal methods for safety and concludes with some widely adopted standards for the certification of safety-critical systems.

Providing an in-depth and hands-on view of the application of formal techniques to advanced and critical safety assessments in a variety of industrial sectors, such as transportation, avionics and aerospace, and nuclear power, Design and Safety Assessment of Critical Systems allows anyone with a basic background in mathematics or computer science to move confidently into this advanced arena of safety assessment.

In view of the incessant growth of data and knowledge and the continued diversifi- tion of information dissemination on a global scale, scalability has become a ma- stream research area in computer science and information systems. The ICST INFO- SCALE conference is one of the premier forums for presenting new and exciting research related to all aspects of scalability, including system architecture, resource management, data management, networking, and performance. As the fourth conf- ence in the series, INFOSCALE 2009 was held in Hong Kong on June 10 and 11, 2009. The articles presented in this volume focus on a wide range of scalability issues and new approaches to tackle problems arising from the ever-growing size and c- plexity of information of all kind. More than 60 manuscripts were submitted, and the Program Committee selected 22 papers for presentation at the conference. Each s- mission was reviewed by three members of the Technical Program Committee.

Das 21. Fachgesprach Autonome Mobile Systeme (AMS 2009) ist ein Forum, das Wissenschaftlerinnen und Wissenschaftlern aus Forschung und Industrie, die auf dem Gebiet der autonomen mobilen Systeme arbeiten, eine Basis fur den Gedankenaustausch bietet und wissenschaftliche Diskussionen sowie Kooperationen auf diesem Forschungsgebiet fordert bzw. initiiert. Inhaltlich finden sich ausgewahlte Beitrage zu den Themen Humanoide Roboter und Flugmaschinen, Perzeption und Sensorik, Kartierung und Lokalisation, Regelung, Navigation, Lernverfahren, Systemarchitekturen sowie der Anwendung von autonomen mobilen Systemen."

In the mid 1990s, researchers began applying Evolutionary Algorithms (EAs) on a kind of computer chip that could dynamically alter the functionality and physicalconnectionsofits circuits. This combinationofEAs withprogrammable electronics (e. g., Field Programmable Gate Arrays (FPGAs) and Field P- grammable Analogue Arrays (FPAAs)) spawned a new ?eld of Evolutionary Computation (EC) called Evolvable Hardware (EH) with its ?rst workshop, - wards Evolvable Hardware, held in Lausanne, Switzerland in October 1995. This workshop was followed by the First International Conference on Evolvable S- tems: From Biology to Hardware (ICES' 96), held inTsukuba, Japanin October 1996. The second ICES was held in Lausanne, September 1998, the third was in Edinburgh, April 2000, the fourth was in Tokyo, October 2001, the ?fth was in Trondheim, March 2003, the sixth was in Sitges, September 2005, and the seventh was in Wuhan, September 2007. Over the years the EH ?eld has expanded beyond the use of EAs on simple electronic devices to encompass many di?erent combinations of EAs and biol- ically inspired algorithms (BIAs) with various physical devices (or simulations of physical devices). Present research in the ?eld of EH can be split into the two related areas of Evolvable HardwareDesign (EHD) and Adaptive Hardware (AH). Evolvable Hardware Design (EHD) is the use of EAs and BIAs for cre- ing physical devices and designs, examples of where EHD has had some success include analogue and digital electronics, antennas, MEMS chips, opticalsystems aswell asquantum circuits.

The 18th International Conference on Inductive Logic Programming was held in Prague, September 10-12, 2008. ILP returned to Prague after 11 years, and it is tempting to look at how the topics of interest have evolved during that time. The ILP community clearly continues to cherish its beloved ?rst-order logic representation framework. This is legitimate, as the work presented at ILP 2008 demonstrated that there is still room for both extending established ILP approaches (such as inverse entailment) and exploring novel logic induction frameworks (such as brave induction). Besides the topics lending ILP research its unique focus, we were glad to see in this year's proceedings a good n- ber of papers contributing to areas such as statistical relational learning, graph mining, or the semantic web. To help open ILP to more mainstream research areas, the conference featured three excellent invited talks from the domains of the semantic web (Frank van Harmelen), bioinformatics (Mark Craven) and cognitive sciences (Josh Tenenbaum). We deliberately looked for speakers who are not directly involved in ILP research. We further invited a tutorial on stat- tical relational learning (Kristian Kersting) to meet the strong demand to have the topic presented from the ILP perspective. Lastly, Stefano Bertolo from the European Commission was invited to give a talk on the ideal niches for ILP in the current EU-supported research on intelligent content and semantics.

Enterprise architecture requires an understanding of all technologies, strategies, and data consumption throughout the enterprise. To this end, one must strive to always broaden knowledge of existing, as well as emerging trends and solutions. As a trade, this role demands an understanding beyond the specificities of technologies and vendor products. An enterprise architect must be versatile with the design and arrangement of elements in an extended network enterprise. Intended for anyone charged with coordinating enterprise architectural design in a small, medium, or large organization, Sustainable Enterprise Architecture helps you explore the various elements of your own particular network environment to develop strategies for mid- to long-term management and sustainable growth. Organized much like a book on structural architecture, this one starts with a solid foundation of frameworks and general guidelines for enterprise governance and design. The book covers common considerations for all enterprises, and then drills down to specific types of technology that may be found in your enterprise. It explores strategies for protecting enterprise resources and examines technologies and strategies that are only just beginning to take place in the modern enterprise network. Each chapter builds on the knowledge and understanding of topics presented earlier in the book to give you a thorough understanding of the challenges and opportunities in managing enterprise resources within a well-designed architectural strategy. Emphasizing only those strategies that weather change, Sustainable Enterprise Architecture shows you how to evaluate your own unique environment and find alignment with the concepts of sustainability and architecture. It gives you the tools to build solutions and policies to protect your enterprise and allow it to provide the greatest organizational value into the future.

This comprehensive account of the concept and practices of deduction is the first to bring together perspectives from philosophy, history, psychology and cognitive science, and mathematical practice. Catarina Dutilh Novaes draws on all of these perspectives to argue for an overarching conceptualization of deduction as a dialogical practice: deduction has dialogical roots, and these dialogical roots are still largely present both in theories and in practices of deduction. Dutilh Novaes' account also highlights the deeply human and in fact social nature of deduction, as embedded in actual human practices; as such, it presents a highly innovative account of deduction. The book will be of interest to a wide range of readers, from advanced students to senior scholars, and from philosophers to mathematicians and cognitive scientists.

Parallel Computing: Methods, Algorithms and Applications presents a collection of original papers presented at the international meeting on parallel processing, methods, algorithms, and applications at Verona, Italy in September 1989.

The increasing adoption of Business Process Management (BPM) has inspired pioneering software architects and developers to effectively leverage BPM-based software and process-centric architecture (PCA) to create software systems that enable essential business processes. Reflecting this emerging trend and evolving field, Process-Centric Architecture for Enterprise Software Systems provides a complete and accessible introduction explaining this architecture.
The text presents, in detail, the analysis and design principles used in process-centric architecture. Illustrative examples demonstrate how to architect and design enterprise systems based on the business processes central to your organization. It covers the architectural aspects of business process management, the evolution of IT systems in enterprises, the importance of a business process focus, the role of workflows, business rules, enterprise application integration, and business process modeling languages such as WS-BPEL and BPML. It also investigates:

• Fundamental concepts of process-centric architecture style
• The PCA approach to architecting enterprise IT systems
• Business process driven applications and integration
• Two case studies that illustrate how to architect and design enterprise applications based on PCA
• SOA in the context of process-centric architecture
• Standards, technologies, and infrastructure behind PCA

Explaining how to architect enterprise systems using a BPMS technology platform, J2EE components, and Web services, this forward-looking book will empower you to create systems centered on business processes and make today s enterprise processes successful and agile."

This volume contains the proceedings of the 21st International Conference on Computer-Aided Veri?cation (CAV) held in Grenoble, France, between June 28 and July 2, 2009. CAV is dedicated to the advancement of the theory and practice of computer-aided formal analysis methods for hardware and software systems. Its scope ranges from theoretical results to concrete applications, with an emphasis on practical veri?cation tools and the underlying algorithms and techniques. Everyinstanceofaconferenceisspecialinitsownway.ThisCAVisspecialfor at least two reasons: ?rst, it took place in Grenoble, the place where the CAV series started 20 years ago. Secondly, there was a particularly large number of paper submissions: 135 regular papers and 34 tool papers, summing up to 169 submissions. They all went through an active review process, with each submissionreviewedbyfourmembersoftheProgramCommittee.Wealsosought external reviews from experts in certain areas. Authors had the opportunity to respond to the initial reviews during an author response period. All these inputs wereusedbytheProgramCommitteeinselectinga?nalprogramwith36 regular papers and 16 tool papers. In addition to the presentation of these papers, the program included the following: - Four invited tutorials: Rachid Guerraoui (EPFL Lausanne, Switzerland): Transactional M- ory: Glimmer of a Theory. Jaeha Kim (Stanford, USA): Mixed-Signal System Veri?cation: A High- Speed Link Example. Jean Krivine (Institut des Hautes Etudes Scienti?ques, France): M- elling Epigenetic Information Maintenance: A Kappa Tutorial. JosephSifakis (CNRS-VERIMAG, France): Component-BasedConstr- tion of Real-Time Systems in BIP."

For manyyears, the idea of recon?gurablehardwaresystems hasrepresentedthe Holy Grail for computer systemdesigners.It has been recognizedfor a long time that the microprocessor provides high ?exibility but at a very low performance merit in terms of MIPS/W or other such measures. Recon?gurable systems are thus attractive as they can be con?gured to provide the best match for the computational requirements at that speci?c time, giving much better area - speed - power performance. However, the practicalities of achieving such a recon?gurable system are - merous andrequirethe developmentof: suitable recon?gurablehardwareto s- portthe dynamicbehavior;programmingtoolsto allowthe dynamicbehavior of the recon?gurability to be modelled; programming languages to support rec- ?guration;andveri?cationtechniquesthatcandemonstratethatrecon?guration hashappenedcorrectlyateachstage.Whiletheproblemsaremany, theexistence and development of technologies such as the multi-core processor architecture, recon?gurable computing architectures, and application-speci?c processors s- gest there is a strong desire for recon?gurable systems. Moreover, FPGAs also provide the ideal platforms for the development of such platforms. The major motivation behind the International Workshop on Applied - con?gurable Computing (ARC) series is to create a forum for presenting and discussing on-going research e?orts in applied recon?gurable computing. The workshop also focuses on compiler and mapping techniques, and new recon- urablecomputingarchitectures.Theseriesofeditionsstartedin2005inAlgarve, Portugal, followed by the 2006 workshop in Delft, The Netherlands, and last year's workshop in Mangaratiba, Rio de Janeiro, Brazil. As in previous years, selectedpapershavebeenpublished asa SpringerLNCS(LectureNotes in C- puter Science) volume.

OpenMP is an application programming interface (API) that is widely accepted as a de facto standard for high-level shared-memory parallel programming. It is a portable, scalable programming model that provides a simple and ?exible interface for developing shared-memory parallel applications in Fortran, C, and C++. Since its introduction in 1997, OpenMP has gained support from the - jority of high-performance compiler and hardware vendors. Under the direction of the OpenMP Architecture Review Board (ARB), the OpenMP speci?cation is undergoing further improvement. Active research in OpenMP compilers, r- time systems, tools, and environments continues to drive OpenMP evolution.To provideaforumforthedisseminationandexchangeofinformationaboutand- periences with OpenMP, the community of OpenMP researchersand developers in academia and industry is organized under cOMPunity (www.compunity.org). This organization has held workshops on OpenMP since 1999. This book contains the proceedings of the 5th International Workshop on OpenMP held in Dresden in June 2009. With sessions on tools, benchmarks, applications, performance and runtime environments it covered all aspects of the current use of OpenMP. In addition, several contributions presented p- posed extensions to OpenMP and evaluated reference implementations of those extensions. An invited talk provided the details on the latest speci?cation dev- opment inside the Architecture Review Board. Together with the two keynotes about OpenMP on hardware accelerators and future generation processors it demonstrated that OpenMP is suitable for future generation systems.

This volume contains the proceedings of the 12th International Conference on Hybrid Systems Computation and Control (HSCC 2009) held in San Francisco, CaliforniaduringApril13-15,2009. Theannualconferenceonhybridsystems- cuses on researchin embedded, reactive systems involving the interplay between discrete switching and continuous dynamics. HSCC is a forum for academic and industrial researchers and practitioners to exchange information on the latest advancements, both practical and theoretical, in the design, analysis, control, optimization, and implementation of hybrid systems. HSCC 2009 was the 12th in a series of successful meetings. Previous versions wereheld in Berkeley(1998), Nijmegen (1999), Pittsburgh(2000), Rome (2001), PaloAlto (2002), Prague(2003), Philadelphia (2004), Zurich (2005), Santa B- bara (2006), Pisa (2007), and St. Louis (2008). HSCC 2009 was part of the 2nd Cyber-Physical Systems Week (CPSWeek), whichconsistedoftheco-locationofHSCCwiththeInternationalConferenceon Information Processing in Sensor Networks (IPSN) and the Real-Time and - bedded Technology and Applications Symposium (RTAS). Through CPSWeek, the three conferences had joint invited speakers, poster sessions, and joint - cial events. In addition to the workshops sponsored by CPSWeek, HSCC 2009 sponsored two workshops: - NSV II: Second International Workshop on Numerical Software Veri?cation - HSCB 2009: Hybrid Systems Approaches to Computational Biology We would like to thank the authors of submitted papers, the Program C- mittee members, the additional reviewers, the workshop organizers, and the HSCC Steering Committee members for their help in composing a strong p- gram. We also thank the CPSWeek Organizing Committee, in particular Rajesh Gupta, for their strenuous work in handling the local arrangemen

1 2 Per Stenstro ..m and David Whalley 1 Chalmers University of Technology, Sweden 2 Florida State University, U.S.A. In January2007,the secondedition in the series of International Conferenceson High-Performance Embedded Architectures andCompilers (HiPEAC'2007)was held in Ghent,Belgium.We were fortunate to attract around70 submissions of whichonly19wereselected forpresentation.Amongthese,weaskedtheauthors ofthe?vemost highly rated contributionsto make extended versions ofthem. They all accepted to do that andtheirarticles appear in this section ofthe second volume. The?rstarticlebyKeramidas,Xekalakis,andKaxirasfocusesontheincreased power consumption in set-associativecaches.They presenta novel approach to reduce dynamicpower that leverages on the previously proposed cache decay approach that has been shown to reduce static (or leakage) power. In the secondarticlebyMagarajan,Gupta,andKrishnaswamythe focus ison techniques to encrypt data in memory to preservedata integrity. The problem with previous techniques is that the decryption latency ends up on the critical memory access path. Especially in embedded processors,caches are small and it isdi?cultto hide the decryption latency. The authors propose a compiler-based strategy that manages to reduce the impact of the decryption time signi?cantly. The thirdarticlebyKluyskensandEeckhoutfocusesondetailedarchitectural simulation techniques.It is well-known that they are ine?cientandaremedy to the problem isto use sampling.When usingsampling,onehastowarm up memory structures such as caches andbranch predictors.Thispaper introduces a noveltechnique calledBranchHistoryMatchingfore?cient warmupofbranch predictors. The fourth articlebyBhadauria,McKee,Singh, and Tyson focuses on static power consumptioninlarge caches.Theyintroduce a reuse-distance drowsy cache mechanism that issimpleas well as e?ective in reducingthestaticpower in caches.