Embedded Processor-Based Self-Test is a guide to self-testing strategies for embedded processors. Embedded processors are regularly used today in most System-on-Chips (SoCs). Testing of microprocessors and embedded processors has always been a challenge because most traditional testing techniques fail when applied to them. This is due to the complex sequential structure of processor architectures, which consists of high performance datapath units and sophisticated control logic for performance optimization. Structured Design-for-Testability (DfT) and hardware-based self-testing techniques, which usually have a non-trivial impact on a circuit's performance, size and power, can not be applied without serious consideration and careful incorporation into the processor design.

Embedded Processor-Based Self-Test shows how the powerful embedded functionality that processors offer can be utilized as a self-testing resource. Through a discussion of different strategies the book emphasizes on the emerging area of Software-Based Self-Testing (SBST). SBST is based on the idea of execution of embedded software programs to perform self-testing of the processor itself and its surrounding blocks in the SoC. SBST is a low-cost strategy in terms of overhead (area, speed, power), development effort and test application cost, as it is applied using low-cost, low-speed test equipment.

Embedded Processor-Based Self-Test can be used by designers, DfT engineers, test practitioners, researchers and students working on digital testing, and in particular processor and SoC test. This book sets the framework for comparisons among different SBST methodologies by discussing key requirements. It presents successful applications of SBST to a number of embedded processors of different complexities and instruction set architectures.

The primary objective of this book is to teach the architectures, design principles, and troubleshooting techniques of a LAN. This will be imparted through the presentation of a broad scope of data and computer communication standards, real-world inter-networking techniques, architectures, hardware, software, protocols, technologies and services as they relate to the design, implementation and troubleshooting of a LAN. The logical and physical design of hardware and software is not the only process involved in the design and implementation of a LAN. The latter also encompasses many other aspects including making the business case, compiling the requirements, choosing the technology, planning for capacity, selecting the vendor, and weighing all the issues before the actual design begins.

ESL or "Electronic System Level" is a buzz word these days, in the electronic design automation (EDA) industry, in design houses, and in the academia. Even though numerous trade magazine articles have been written, quite a few books have been published that have attempted to de?ne ESL, it is still not clear what exactly it entails. However, what seems clear to every one is that the "Register Transfer Level" (RTL) languages are not adequate any more to be the design entry point for today's and tomorrow's complex electronic system design. There are multiple reasons for such thoughts. First, the c- tinued progression of the miniaturization of the silicon technology has led to the ability of putting almost a billion transistors on a single chip. Second, applications are becoming more and more complex, and integrated with c- munication, control, ubiquitous and pervasive computing, and hence the need for ever faster, ever more reliable, and more robust electronic systems is pu- ing designers towards a productivity demand that is not sustainable without a fundamental change in the design methodologies. Also, the hardware and software functionalities are getting interchangeable and ability to model and design both in the same manner is gaining importance. Given this context, we assume that any methodology that allows us to model an entire electronic system from a system perspective, rather than just hardware with discrete-event or cycle based semantics is an ESL method- ogy of some kind.

System-on-Chip Methodologies & Design Languages brings together a selection of the best papers from three international electronic design language conferences in 2000. The conferences are the Hardware Description Language Conference and Exhibition (HDLCon), held in the Silicon Valley area of USA; the Forum on Design Languages (FDL), held in Europe; and the Asia Pacific Chip Design Language (APChDL) Conference. The papers cover a range of topics, including design methods, specification and modeling languages, tool issues, formal verification, simulation and synthesis. The results presented in these papers will help researchers and practicing engineers keep abreast of developments in this rapidly evolving field.

xv From the Old to the New xvii Acknowledgments xxi 1 Verilog - A Tutorial Introduction 1 Getting Started 2 A Structural Description 2 Simulating the binaryToESeg Driver 4 Creating Ports For the Module 7 Creating a Testbench For a Module 8 11 Behavioral Modeling of Combinational Circuits Procedural Models 12 Rules for Synthesizing Combinational Circuits 13 14 Procedural Modeling of Clocked Sequential Circuits Modeling Finite State Machines 15 Rules for Synthesizing Sequential Systems 18 Non-Blocking Assignment ("

Memory Design Techniques for Low Energy Embedded Systems centers one of the most outstanding problems in chip design for embedded application. It guides the reader through different memory organizations and technologies and it reviews the most successful strategies for optimizing them in the power and performance plane.

Data Access and Storage Management for Embedded Programmable Processors gives an overview of the state-of-the-art in system-level data access and storage management for embedded programmable processors. The targeted application domain covers complex embedded real-time multi-media and communication applications. Many of these applications are data-dominated in the sense that their cost related aspects, namely power consumption and footprint are heavily influenced (if not dominated) by the data access and storage aspects. The material is mainly based on research at IMEC in this area in the period 1996-2001. In order to deal with the stringent timing requirements and the data dominated characteristics of this domain, we have adopted a target architecture style that is compatible with modern embedded processors, and we have developed a systematic step-wise methodology to make the exploration and optimization of such applications feasible in a source-to-source precompilation approach.
In a first part of the book, we introduce the context and motivation, followed by a once-over-lightly view of the entire approach, illustrated on a relevant driver from the targeted application domain. In part 2, we show how source-to-source code transformations play a crucial role in the solution of the earlier mentioned data transfer and storage bottleneck in modern processor architectures for multi-media and telecommunication applications. This is especially true for embedded applications where cost issues like memory footprint and power consumption are vital. It is also shown that many of these code transformations can be defined in a platform-independent way. The resulting optimized code behaves betteron any of the modern platforms. The steps include global data-flow and loop transformations, data reuse decisions, high-level estimators and the link with parallelisation and multi-processor partitioning. In part 3 we discuss our research efforts relating to the mapping of embedded applications to specific memory organisations in embedded programmable processors. In a traditional processor-based environment, compilers perform memory optimizations assuming a fully fixed hardware target architecture with only maximal performance in mind. However, in an embedded context also cost issues and especially power consumption and memory footprint play a dominant role too. Usually the timing requirements are given and the application designer is mostly interested in the trade-off between timing characteristics of the different application tasks and their cost effects. For this purpose Pareto type trade-off curves are the most suitable vehicle to address this design problem. The steps involved here include the storage cycle budget distribution, support of modern memory architectures like SDRAMs, and cache related issues.

This text helps the reader generate clear, effective documentation that is tailored to the information requirements of the end-user. Written for technical writers and their managers, quality assurance experts, and software engineers, the book describes a user-centered information design method (UCID) that should help ensure documentation conveys significant information for the user. The UCID shows how to: integrate the four major information components of a software system - user interface labels, messages, online and printed documentation; make sure these elements work together to improve usability; deploy iterative design and prototyping procedures that minimize flaws and save time and money; and guide technical writers effectively.

This book brings together research on numerical methods adapted for Graphics Processing Units (GPUs). It explains recent efforts to adapt classic numerical methods, including solution of linear equations and FFT, for massively parallel GPU architectures. This volume consolidates recent research and adaptations, covering widely used methods that are at the core of many scientific and engineering computations. Each chapter is written by authors working on a specific group of methods; these leading experts provide mathematical background, parallel algorithms and implementation details leading to reusable, adaptable and scalable code fragments. This book also serves as a GPU implementation manual for many numerical algorithms, sharing tips on GPUs that can increase application efficiency. The valuable insights into parallelization strategies for GPUs are supplemented by ready-to-use code fragments. Numerical Computations with GPUs targets professionals and researchers working in high performance computing and GPU programming. Advanced-level students focused on computer science and mathematics will also find this book useful as secondary text book or reference.

Holographic Data Storage is an outstanding reference book on an exciting topic reaching out to the 21st century's key technologies. The editors, Hans J. Coufal (IBM), Demetri Psaltis (CalTech), and Glenn Sincerbox (University of Arizona), together with leading experts in this area of research from both academic research and industry, bring together the latest knowledge on this technique. The book starts with an introduction on the history and fundamentals, multiplexing methods, and noise sources. The following chapters describe in detail recording media, components, channels, platforms for demonstration, and competing technologies such as classical hard disks or optical disks. More than 700 references make this book the ultimate source of information for the years to come. The book is intended for physicists, optical engineers, and executives alike.

With the advent of portable and autonomous computing systems, power con sumption has emerged as a focal point in many research projects, commercial systems and DoD platforms. One current research initiative, which drew much attention to this area, is the Power Aware Computing and Communications (PAC/C) program sponsored by DARPA. Many of the chapters in this book include results from work that have been supported by the PACIC program. The performance of computer systems has been tremendously improving while the size and weight of such systems has been constantly shrinking. The capacities of batteries relative to their sizes and weights has been also improv ing but at a rate which is much slower than the rate of improvement in computer performance and the rate of shrinking in computer sizes. The relation between the power consumption of a computer system and it performance and size is a complex one which is very much dependent on the specific system and the technology used to build that system. We do not need a complex argument, however, to be convinced that energy and power, which is the rate of energy consumption, are becoming critical components in computer systems in gen eral, and portable and autonomous systems, in particular. Most of the early research on power consumption in computer systems ad dressed the issue of minimizing power in a given platform, which usually translates into minimizing energy consumption, and thus, longer battery life."

Fault-tolerant control aims at a gradual shutdown response in automated systems when faults occur. It satisfies the industrial demand for enhanced availability and safety, in contrast to traditional reactions to faults, which bring about sudden shutdowns and loss of availability. The book presents effective model-based analysis and design methods for fault diagnosis and fault-tolerant control. Architectural and structural models are used to analyse the propagation of the fault through the process, to test the fault detectability and to find the redundancies in the process that can be used to ensure fault tolerance. It also introduces design methods suitable for diagnostic systems and fault-tolerant controllers for continuous processes that are described by analytical models of discrete-event systems represented by automata. The book is suitable for engineering students, engineers in industry and researchers who wish to get an overview of the variety of approaches to process diagnosis and fault-tolerant control. The authors have extensive teaching experience with graduate and PhD students, as well as with industrial experts. Parts of this book have been used in courses for this audience. The authors give a comprehensive introduction to the main ideas of diagnosis and fault-tolerant control and present some of their most recent research achievements obtained together with their research groups in a close cooperation with European research projects. The third edition resulted from a major re-structuring and re-writing of the former edition, which has been used for a decade by numerous research groups. New material includes distributed diagnosis of continuous and discrete-event systems, methods for reconfigurability analysis, and extensions of the structural methods towards fault-tolerant control. The bibliographical notes at the end of all chapters have been up-dated. The chapters end with exercises to be used in lectures.

Hardware Design and Petri Nets presents a summary of the state of the art in the applications of Petri nets to designing digital systems and circuits. The area of hardware design has traditionally been a fertile field for research in concurrency and Petri nets. Many new ideas about modelling and analysis of concurrent systems, and Petri nets in particular, originated in theory of asynchronous digital circuits. Similarly, the theory and practice of digital circuit design have always recognized Petri nets as a powerful and easy-to-understand modelling tool. The ever-growing demand in the electronic industry for design automation to build various types of computer-based systems creates many opportunities for Petri nets to establish their role of a formal backbone in future tools for constructing systems that are increasingly becoming distributed, concurrent and asynchronous. Petri nets have already proved very effective in supporting algorithms for solving key problems in synthesis of hardware control circuits. However, since the front end to any realistic design flow in the future is likely to rely on more pragmatic Hardware Description Languages (HDLs), such as VHDL and Verilog, it is crucial that Petri nets are well interfaced to such languages. Hardware Design and Petri Nets is divided into five parts, which cover aspects of behavioral modelling, analysis and verification, synthesis from Petri nets and STGs, design environments based on high-level Petri nets and HDLs, and finally performance analysis using Petri nets. Hardware Design and Petri Nets serves as an excellent reference source and may be used as a text for advanced courses on the subject.

This timely text presents a comprehensive overview of fault tolerance techniques for high-performance computing (HPC). The text opens with a detailed introduction to the concepts of checkpoint protocols and scheduling algorithms, prediction, replication, silent error detection and correction, together with some application-specific techniques such as ABFT. Emphasis is placed on analytical performance models. This is then followed by a review of general-purpose techniques, including several checkpoint and rollback recovery protocols. Relevant execution scenarios are also evaluated and compared through quantitative models. Features: provides a survey of resilience methods and performance models; examines the various sources for errors and faults in large-scale systems; reviews the spectrum of techniques that can be applied to design a fault-tolerant MPI; investigates different approaches to replication; discusses the challenge of energy consumption of fault-tolerance methods in extreme-scale systems.

2 Concept ( Tools * Specification ( Tools + Design Stages ( Tools * Implementation ( Tools Figure 1-1. A nominal, multi-stage development process From that beginning, we have progressed to the point where the EDA community at large, including both users and developers of the tools, are interested in more unified environments. Here, the notion is that the tools used at the various stages in the development process need to be able to complement each other, and to communicate with one another efficiently using effective file exchange capabilities. Furthermore, the idea of capturing all the tool support needed for an EDA development into a unified support environment is now becoming a reality. This reality is evidenced by some of the EDA suites we now see emerging, wherein several tool functions are integrated under a common graphical user interface (GUI), with supporting file exchange and libraries to enable all tool functions to operate effectively and synergistically. This concept, which we illustrate in Figure 1- 2, is the true future ofEDA.

The essentials of comprehensible specifications of business and of system artefacts ought to be used by, and therefore understandable to, all customers of these specifications - business subject matter experts, decision makers, analysts, IT architects and developers. These documents have to be understood in the same manner by all stakeholders. And, as C.A.R. Hoare observed, only abstraction "enables a chief programmer or manager to exert real technical control over his teams, without delving into the morass of technical detail with which his programmers are often tempted to overwhelm him."

The book brings together theoreticians and practitioners to report their experience with making semantics precise, clear, concise and explicit in business specifications, business designs, and system specifications. It includes both theoretical and very pragmatic papers based on solid and clearly specified foundations. These seemingly different papers address different aspects of a single problem - they are all about understanding of business enterprises and of information systems (computer-based or not) that these enterprises rely upon. A substantial number of papers demonstrate that good business (and IT) specifications ought to start with the stable basics of the relevant business domains, thus providing a foundation for describing and evaluating the details of apparently "always changing" requirements.

Promptly growing demand for telecommunication services and information interchange has led to the fact that communication became one of the most dynamical branches of an infrastructure of a modern society. The book introduces to the bases of classical MDP theory; problems of a finding optimal CAC in models are investigated and various problems of improvement of characteristics of traditional and multimedia wireless communication networks are considered together with both classical and new methods of theory MDP which allow defining optimal strategy of access in teletraffic systems. The book will be useful to specialists in the field of telecommunication systems and also to students and post-graduate students of corresponding specialties.

This comprehensive survey on the state of the art of SystemC in industry and research is organised into 11 self-contained chapters. Selected SystemC experts present their approaches in the domains of modelling, analysis and synthesis, ranging from mixed signal and discrete system to embedded software.

As multimedia data advances in technology and becomes more complex, the hybridization of soft computing tools allows for more robust and safe solutions in data processing and analysis. Quantum-Inspired Intelligent Systems for Multimedia Data Analysis provides emerging research on techniques used in multimedia information processing using intelligent paradigms including swarm intelligence, neural networks, and deep learning. While highlighting topics such as clustering techniques, neural network architecture, and text data processing, this publication explores the methods and applications of computational intelligent tools. This book is an important resource for academics, computer engineers, IT professionals, students, and researchers seeking current research in the field of multimedia data processing and quantum intelligent systems.

Function Architecture Co-Design is a new paradigm for the design and implementation of embedded systems. Function/Architecture Optimization and Co-Design of Embedded Systems presents the authors' work in developing a function/architecture optimization and co-design formal methodology and framework for control-dominated embedded systems. The approach incorporates both data flow and control optimizations performed on a suitable novel intermediate design task representation. The aim is not only to enhance productivity of the designer and system developer, but also to improve quality of the final synthesis outcome. Function/Architecture Optimization and Co-Design of Embedded Systems discusses the proposed function/architecture co-design methodology, focusing on design representation, optimization, validation, and synthesis. Throughout the text, the difference between behavior specification and implementation is emphasized. The current need in co-design to move from synthesis-based technology to compiler-based technology is pointed out. The authors describe and show how performing data flow and control optimizations at the high abstraction level can lead to significant size and performance improvements in both the synthesized hardware and software. The work builds on bodies of research in the silicon and software compilation domains. The aforementioned techniques are specialized to the embedded systems domain. It is recognized that guided optimization can be applied on the internal design representation, no matter what the abstraction level, and need not be restricted to the final stages of software assembly code generation, or hardware synthesis. Function/Architecture Optimization and Co-Design of Embedded Systems will be of primary interest to researchers, developers, and professionals in the field of embedded systems design.

This guide provides a comprehensive overview of High Performance Computing (HPC) to equip students with a full skill set including cluster setup, network selection, and a background of supercomputing competitions. It covers the system, architecture, evaluating approaches, and other practical supercomputing techniques. As the world's largest supercomputing hackathon, the ASC Student Supercomputer Challenge has attracted a growing number of new talent to supercomputing and has greatly promoted communications in the global HPC community. Enclosed in this book, readers will also find how to analyze and optimize supercomputing systems and applications in real science and engineering cases.

The purpose of this book is to introduce VHSIC Hardware Description Lan guage (VHDL) and its use for synthesis. VHDL is a hardware description language which provides a means of specifying a digital system over different levels of abstraction. It supports behavior specification during the early stages of a design process and structural specification during the later implementation stages. VHDL was originally introduced as a hardware description language that per mitted the simulation of digital designs. It is now increasingly used for design specifications that are given as the input to synthesis tools which translate the specifications into netlists from which the physical systems can be built. One problem with this use of VHDL is that not all of its constructs are useful in synthesis. The specification of delay in signal assignments does not have a clear meaning in synthesis, where delays have already been determined by the im plementationtechnolo y. VHDL has data-structures such as files and pointers, useful for simulation purposes but not for actual synthesis. As a result synthe sis tools accept only subsets of VHDL. This book tries to cover the synthesis aspect of VHDL, while keeping the simulation-specifics to a minimum. This book is suitable for working professionals as well as for graduate or under graduate study. Readers can view this book as a way to get acquainted with VHDL and how it can be used in modeling of digital designs."

The Verilog hardware description language provides the ability to describe digital and analog systems for design concepts and implementation. It was developed originally at Gateway Design and implemented there. Now it is an open standard of IEEE and Open Verilog International and is supported by many tools and processes. The Complete Verilog Book introduces the language and describes it in a comprehensive manner. In The Complete Verilog Book, each feature of the language is described using semantic introduction, syntax and examples. A chapter on semantics explains the basic concepts and algorithms that form the basis of every evaluation and every sequence of evaluations that ultimately provides the meaning or full semantics of the language. The Complete Verilog Book takes the approach that Verilog is not only a simulation language or a synthesis language or a formal method of describing design, but is a totality of all these and covers many aspects not covered before but which are essential parts of any design process using Verilog. The Complete Verilog Book starts with a tutorial introduction. It explains the data types in Verilog HDL, as the object-oriented world knows that the language-constructs and data types are equally important parts of a language. The Complete Verilog Book explains the three views, behavioral, RTL and structural and then describes features in each of these views. The Complete Verilog Book keeps the reader abreast of current developments in the Verilog world such as Verilog-A, cycle simulation, SD, and DCL, and uses IEEE 1364 syntax. The Complete Verilog Book will be useful to all those who want to learn Verilog HDL and to explore its various facets.

Evolutionary Algorithms for Embedded System Design describes how Evolutionary Algorithm (EA) concepts can be applied to circuit and system design - an area where time-to-market demands are critical. EAs create an interesting alternative to other approaches since they can be scaled with the problem size and can be easily run on parallel computer systems. This book presents several successful EA techniques and shows how they can be applied at different levels of the design process. Starting on a high-level abstraction, where software components are dominant, several optimization steps are demonstrated, including DSP code optimization and test generation. Throughout the book, EAs are tested on real-world applications and on large problem instances. For each application the main criteria for the successful application in the corresponding domain are discussed. In addition, contributions from leading international researchers provide the reader with a variety of perspectives, including a special focus on the combination of EAs with problem specific heuristics.

Evolutionary Algorithms for Embedded System Design is an excellent reference for both practitioners working in the area of circuit and system design and for researchers in the field of evolutionary concepts.

The book presents the state of the art in high-performance computing and simulation on modern supercomputer architectures. It explores general trends in hardware and software development, and then focuses specifically on the future of high-performance systems and heterogeneous architectures. It also covers applications such as computational fluid dynamics, material science, medical applications and climate research and discusses innovative fields like coupled multi-physics or multi-scale simulations. The papers included were selected from the presentations given at the 20th Workshop on Sustained Simulation Performance at the HLRS, University of Stuttgart, Germany in December 2015, and the subsequent Workshop on Sustained Simulation Performance at Tohoku University in February 2016.