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Books > Professional & Technical > Energy technology & engineering > Electrical engineering
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Verification by Error Modeling - Using Testing Techniques in Hardware Verification (Paperback, Softcover reprint of the original 1st ed. 2003)
Loot Price: R3,020
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Verification by Error Modeling - Using Testing Techniques in Hardware Verification (Paperback, Softcover reprint of the original 1st ed. 2003)
Series: Frontiers in Electronic Testing, 25
Expected to ship within 10 - 15 working days
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Verification presents the most time-consuming task in the
integrated circuit design process. The increasing similarity
between implementation verification and the ever-needed task of
providing vectors for manufacturing fault testing is tempting many
professionals to combine verification and testing efforts.
This book presents the basis for reusing the test vector generation
and simulation for the purpose of implementation verification, to
result in a significant timesaving. The book brings the results in
the direction of merging manufacturing test vector generation and
verification. It first discusses error fault models suitable for
approaching the verification by testing methods. Then, it
elaborates a proposal for an implicit fault model that uses the
Arithmetic Transform representation of a circuit and the faults.
Presented is the fundamental link between the error size and the
test vector size, which allows parametrizable verification by test
vectors. Furthermore, the test vector set is sufficient not only
for detecting, but also for diagnosing and correcting the design
errors.
The practical use of any such simulation-based verification scheme
can be seriously impaired by redundant faults, that otherwise
require exhaustive simulations. The redundant fault identification
methods are presented that are well suited for the type of faults
considered. Finally, the same representation can be used to augment
and expand the formal verification schemes that are to be used in
conjunction with the simulation-based verification.
The primary audience for Verification by Error Modeling includes
researchers in verification and testing, managers in charge of
verification of test and practicing engineers. Due to its
comprehensive coverage of background topics, the book can also be
used for teaching courses on verification and test topics.
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