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Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits (Paperback, Softcover reprint of hardcover 2nd ed. 2007) Loot Price: R5,444
Discovery Miles 54 440
Repayment Terms: R510 pm x 12*
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Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits (Paperback, Softcover reprint of hardcover 2nd ed. 2007): Manoj...

Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits (Paperback, Softcover reprint of hardcover 2nd ed. 2007)

Manoj Sachdev, Jose Pineda De Gyvez

Series: Frontiers in Electronic Testing, 34

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Loot Price R5,444 Discovery Miles 54 440 | Repayment Terms: R510 pm x 12*

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The 2nd edition of defect oriented testing has been extensively updated. New chapters on Functional, Parametric Defect Models and Inductive fault Analysis and Yield Engineering have been added to provide a link between defect sources and yield. The chapter on RAM testing has been updated with focus on parametric and SRAM stability testing. Similarly, newer material has been incorporated in digital fault modeling and analog testing chapters. The strength of Defect Oriented Testing for nano-Metric CMOS VLSIs lies in its industrial relevance.

General

Imprint: Springer-Verlag New York
Country of origin: United States
Series: Frontiers in Electronic Testing, 34
Release date: November 2010
First published: 2007
Authors: Manoj Sachdev • Jose Pineda De Gyvez
Dimensions: 235 x 155 x 18mm (L x W x T)
Format: Paperback
Pages: 328
Edition: Softcover reprint of hardcover 2nd ed. 2007
ISBN-13: 978-1-4419-4285-2
Categories: Books > Professional & Technical > Technology: general issues > Technical design > General
Books > Professional & Technical > Energy technology & engineering > Electrical engineering > General
Books > Professional & Technical > Electronics & communications engineering > Electronics engineering > Circuits & components
LSN: 1-4419-4285-8
Barcode: 9781441942852

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