|
Showing 1 - 12 of
12 matches in All Departments
This book describes new and effective methodologies for modeling,
analyzing and mitigating cell-internal signal electromigration in
nanoCMOS, with significant circuit lifetime improvements and no
impact on performance, area and power. The authors are the first to
analyze and propose a solution for the electromigration effects
inside logic cells of a circuit. They show in this book that an
interconnect inside a cell can fail reducing considerably the
circuit lifetime and they demonstrate a methodology to optimize the
lifetime of circuits, by placing the output, Vdd and Vss pin of the
cells in the less critical regions, where the electromigration
effects are reduced. Readers will be enabled to apply this
methodology only for the critical cells in the circuit, avoiding
impact in the circuit delay, area and performance, thus increasing
the lifetime of the circuit without loss in other characteristics.
This book describes new and effective methodologies for modeling,
analyzing and mitigating cell-internal signal electromigration in
nanoCMOS, with significant circuit lifetime improvements and no
impact on performance, area and power. The authors are the first to
analyze and propose a solution for the electromigration effects
inside logic cells of a circuit. They show in this book that an
interconnect inside a cell can fail reducing considerably the
circuit lifetime and they demonstrate a methodology to optimize the
lifetime of circuits, by placing the output, Vdd and Vss pin of the
cells in the less critical regions, where the electromigration
effects are reduced. Readers will be enabled to apply this
methodology only for the critical cells in the circuit, avoiding
impact in the circuit delay, area and performance, thus increasing
the lifetime of the circuit without loss in other characteristics.
Recent years have seen rapid strides in the level of sophistication
of VLSI circuits. On the performance front, there is a vital need
for techniques to design fast, low-power chips with minimum area
for increasingly complex systems, while on the economic side there
is the vastly increased pressure of time-to-market. These pressures
have made the use of CAD tools mandatory in designing complex
systems. Timing Analysis and Optimization of Sequential Circuits
describes CAD algorithms for analyzing and optimizing the timing
behavior of sequential circuits with special reference to
performance parameters such as power and area. A unified approach
to performance analysis and optimization of sequential circuits is
presented. The state of the art in timing analysis and optimization
techniques is described for circuits using edge-triggered or
level-sensitive memory elements. Specific emphasis is placed on two
methods that are true sequential timing optimizations techniques:
retiming and clock skew optimization.Timing Analysis and
Optimization of Sequential Circuits covers the following topics: *
Algorithms for sequential timing analysis * Fast algorithms for
clock skew optimization and their applications * Efficient
techniques for retiming large sequential circuits * Coupling
sequential and combinational optimizations. Timing Analysis and
Optimization of Sequential Circuits is written for graduate
students, researchers and professionals in the area of CAD for VLSI
and VLSI circuit design.
The automation of layout synthesis design under stringent timing
specifications is essential for state-of-the-art VLSI circuits and
systems design. Especially, the timing-driven layout synthesis with
optimal placement and routing of transistors with proper sizing is
most critical in view of the chip area, interconnection parasitics,
circuit delay and power dissipation. This book presents a
systematic and unified view of the layout synthesis problem with a
strong focus on CMOS technology. The criticality of RC parasitics
in the interconnects and the optimal sizing of both p-channel and
n-channel translators are illustrated for motivation. Following the
motivation, the problems of modeling circuit delays and translator
sizing are formulated and solved with mathematical rigor. Various
delay models for CMOS circuits are discussed to account for
realistic interconnection parasitics, the effect of transistor
sizes, and also the input slew rates. Also many of the efficient
transistor sizing algorithms are critically reviewed and the most
recent transistor sizing algorithm based on convex programming
techniques is introduced.For design automation of the rigorous CMOS
layout synthesis, an integrated system that employs a suite of
functional modules is introduced for step-by-step illustration of
the design optimization process that produces highly compact CMOS
layouts that meet user-specified timing and logical netlist
requirements. Through most rigorous discussion of the essential
design automation process steps and important models and algorithms
this book presents a unified systems approach that can be practiced
for high-performance CMOS VLSI designs. This book serves as an
excellent reference, and can be used as text in advanced courses
covering VLSI design, especially for design automation of physical
design.
Introduction The exponential scaling of feature sizes in
semiconductor technologies has side-effects on layout optimization,
related to effects such as inter connect delay, noise and
crosstalk, signal integrity, parasitics effects, and power
dissipation, that invalidate the assumptions that form the basis of
previous design methodologies and tools. This book is intended to
sample the most important, contemporary, and advanced layout opti
mization problems emerging with the advent of very deep submicron
technologies in semiconductor processing. We hope that it will
stimulate more people to perform research that leads to advances in
the design and development of more efficient, effective, and
elegant algorithms and design tools. Organization of the Book The
book is organized as follows. A multi-stage simulated annealing
algorithm that integrates floorplanning and interconnect planning
is pre sented in Chapter 1. To reduce the run time, different
interconnect plan ning approaches are applied in different ranges
of temperatures. Chapter 2 introduces a new design methodology -
the interconnect-centric design methodology and its centerpiece,
interconnect planning, which consists of physical hierarchy
generation, floorplanning with interconnect planning, and
interconnect architecture planning. Chapter 3 investigates a
net-cut minimization based placement tool, Dragon, which integrates
the state of the art partitioning and placement techniques."
Introduction The exponential scaling of feature sizes in
semiconductor technologies has side-effects on layout optimization,
related to effects such as inter connect delay, noise and
crosstalk, signal integrity, parasitics effects, and power
dissipation, that invalidate the assumptions that form the basis of
previous design methodologies and tools. This book is intended to
sample the most important, contemporary, and advanced layout opti
mization problems emerging with the advent of very deep submicron
technologies in semiconductor processing. We hope that it will
stimulate more people to perform research that leads to advances in
the design and development of more efficient, effective, and
elegant algorithms and design tools. Organization of the Book The
book is organized as follows. A multi-stage simulated annealing
algorithm that integrates floorplanning and interconnect planning
is pre sented in Chapter 1. To reduce the run time, different
interconnect plan ning approaches are applied in different ranges
of temperatures. Chapter 2 introduces a new design methodology -
the interconnect-centric design methodology and its centerpiece,
interconnect planning, which consists of physical hierarchy
generation, floorplanning with interconnect planning, and
interconnect architecture planning. Chapter 3 investigates a
net-cut minimization based placement tool, Dragon, which integrates
the state of the art partitioning and placement techniques."
Recent years have seen rapid strides in the level of sophistication
of VLSI circuits. On the performance front, there is a vital need
for techniques to design fast, low-power chips with minimum area
for increasingly complex systems, while on the economic side there
is the vastly increased pressure of time-to-market. These pressures
have made the use of CAD tools mandatory in designing complex
systems. Timing Analysis and Optimization of Sequential Circuits
describes CAD algorithms for analyzing and optimizing the timing
behavior of sequential circuits with special reference to
performance parameters such as power and area. A unified approach
to performance analysis and optimization of sequential circuits is
presented. The state of the art in timing analysis and optimization
techniques is described for circuits using edge-triggered or
level-sensitive memory elements. Specific emphasis is placed on two
methods that are true sequential timing optimizations techniques:
retiming and clock skew optimization. Timing Analysis and
Optimization of Sequential Circuits covers the following topics:
Algorithms for sequential timing analysis Fast algorithms for clock
skew optimization and their applications Efficient techniques for
retiming large sequential circuits Coupling sequential and
combinational optimizations. Timing Analysis and Optimization of
Sequential Circuits is written for graduate students, researchers
and professionals in the area of CAD for VLSI and VLSI circuit
design.
The automation of layout synthesis design under stringent timing
specifications is essential for state-of-the-art VLSI circuits and
systems design. Especially, the timing-driven layout synthesis with
optimal placement and routing of transistors with proper sizing is
most critical in view of the chip area, interconnection parasitics,
circuit delay and power dissipation. This book presents a
systematic and unified view of the layout synthesis problem with a
strong focus on CMOS technology. The criticality of RC parasitics
in the interconnects and the optimal sizing of both p-channel and
n-channel translators are illustrated for motivation. Following the
motivation, the problems of modeling circuit delays and translator
sizing are formulated and solved with mathematical rigor. Various
delay models for CMOS circuits are discussed to account for
realistic interconnection parasitics, the effect of transistor
sizes, and also the input slew rates. Also many of the efficient
transistor sizing algorithms are critically reviewed and the most
recent transistor sizing algorithm based on convex programming
techniques is introduced. For design automation of the rigorous
CMOS layout synthesis, an integrated system that employs a suite of
functional modules is introduced for step-by-step illustration of
the design optimization process that produces highly compact CMOS
layouts that meet user-specified timing and logical netlist
requirements. Through most rigorous discussion of the essential
design automation process steps and important models and algorithms
this book presents a unified systems approach that can be practiced
for high-performance CMOS VLSI designs. This book serves as an
excellentreference, and can be used as text in advanced courses
covering VLSI design, especially for design automation of physical
design.
The physical design flow of any project depends upon the size of
the design, the technology, the number of designers, the clock
frequency, and the time to do the design. As technology advances
and design-styles change, physical design flows are constantly
reinvented as traditional phases are removed and new ones are added
to accommodate changes in technology. Handbook of Algorithms for
Physical Design Automation provides a detailed overview of VLSI
physical design automation, emphasizing state-of-the-art
techniques, trends and improvements that have emerged during the
previous decade. After a brief introduction to the modern physical
design problem, basic algorithmic techniques, and partitioning, the
book discusses significant advances in floorplanning
representations and describes recent formulations of the
floorplanning problem. The text also addresses issues of placement,
net layout and optimization, routing multiple signal nets,
manufacturability, physical synthesis, special nets, and designing
for specialized technologies. It includes a personal perspective
from Ralph Otten as he looks back on the major technical milestones
in the history of physical design automation. Although several
books on this topic are currently available, most are either too
broad or out of date. Alternatively, proceedings and journal
articles are valuable resources for researchers in this area, but
the material is widely dispersed in the literature. This handbook
pulls together a broad variety of perspectives on the most
challenging problems in the field, and focuses on emerging problems
and research results.
This book serves both as an introduction to computer architecture
and as a guide to using a hardware description language (HDL) to
design, model and simulate real digital systems. The book starts
with an introduction to Verilog - the HDL chosen for the book since
it is widely used in industry and straightforward to learn. Next,
the instruction set architecture (ISA) for the simple VeSPA (Very
Small Processor Architecture) processor is defined - this is a real
working device that has been built and tested at the University of
Minnesota by the authors. The VeSPA ISA is used throughout the
remainder of the book to demonstrate how behavioural and structural
models can be developed and intermingled in Verilog. Although
Verilog is used throughout, the lessons learned will be equally
applicable to other HDLs. Written for senior and graduate students,
this book is also an ideal introduction to Verilog for practising
engineers.
This book serves both as an introduction to computer architecture
and as a guide to using a hardware description language (HDL) to
design, model and simulate real digital systems. The book starts
with an introduction to Verilog - the HDL chosen for the book since
it is widely used in industry and straightforward to learn. Next,
the instruction set architecture (ISA) for the simple VeSPA (Very
Small Processor Architecture) processor is defined - this is a real
working device that has been built and tested at the University of
Minnesota by the authors. The VeSPA ISA is used throughout the
remainder of the book to demonstrate how behavioural and structural
models can be developed and intermingled in Verilog. Although
Verilog is used throughout, the lessons learned will be equally
applicable to other HDLs. Written for senior and graduate students,
this book is also an ideal introduction to Verilog for practising
engineers.
The physical design flow of any project depends upon the size of
the design, the technology, the number of designers, the clock
frequency, and the time to do the design. As technology advances
and design-styles change, physical design flows are constantly
reinvented as traditional phases are removed and new ones are added
to accommodate changes in technology. Handbook of Algorithms for
Physical Design Automation provides a detailed overview of VLSI
physical design automation, emphasizing state-of-the-art
techniques, trends and improvements that have emerged during the
previous decade. After a brief introduction to the modern physical
design problem, basic algorithmic techniques, and partitioning, the
book discusses significant advances in floorplanning
representations and describes recent formulations of the
floorplanning problem. The text also addresses issues of placement,
net layout and optimization, routing multiple signal nets,
manufacturability, physical synthesis, special nets, and designing
for specialized technologies. It includes a personal perspective
from Ralph Otten as he looks back on the major technical milestones
in the history of physical design automation. Although several
books on this topic are currently available, most are either too
broad or out of date. Alternatively, proceedings and journal
articles are valuable resources for researchers in this area, but
the material is widely dispersed in the literature. This handbook
pulls together a broad variety of perspectives on the most
challenging problems in the field, and focuses on emerging problems
and research results.
|
|