This book focusses on the spacer engineering aspects of novel MOS-based device-circuit co-design in sub-20nm technology node, its process complexity, variability, and reliability issues. It comprehensively explores the FinFET/tri-gate architectures with their circuit/SRAM suitability and tolerance to random statistical variations.

This book focusses on the spacer engineering aspects of novel MOS-based device-circuit co-design in sub-20nm technology node, its process complexity, variability, and reliability issues. It comprehensively explores the FinFET/tri-gate architectures with their circuit/SRAM suitability and tolerance to random statistical variations.

This book constitutes the refereed proceedings of the 21st International Symposium on VLSI Design and Test, VDAT 2017, held in Roorkee, India, in June/July 2017. The 48 full papers presented together with 27 short papers were carefully reviewed and selected from 246 submissions. The papers were organized in topical sections named: digital design; analog/mixed signal; VLSI testing; devices and technology; VLSI architectures; emerging technologies and memory; system design; low power design and test; RF circuits; architecture and CAD; and design verification.

This book constitutes the proceedings of the 26th International Symposium on VLSI Design and Test, VDAT 2022, which took place in Jammu, India, in July 2022. The 32 regular papers and 16 short papers presented in this volume were carefully reviewed and selected from 220 submissions. They were organized in topical sections as follows: Devices and Technology; Sensors; Analog/Mixed Signal; Digital Design; Emerging Technologies and Memory; System Design.

This book constitutes the refereed proceedings of the 23st International Symposium on VLSI Design and Test, VDAT 2019, held in Indore, India, in July 2019. The 63 full papers were carefully reviewed and selected from 199 submissions. The papers are organized in topical sections named: analog and mixed signal design; computing architecture and security; hardware design and optimization; low power VLSI and memory design; device modelling; and hardware implementation.