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Verification Methodology Manual for SystemVerilog (Paperback, 2006 ed.) Loot Price: R2,941
Discovery Miles 29 410
Repayment Terms: R276 pm x 12*
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Verification Methodology Manual for SystemVerilog (Paperback, 2006 ed.): Janick Bergeron, Eduard Cerny, Alan Hunter, Andy...

Verification Methodology Manual for SystemVerilog (Paperback, 2006 ed.)

Janick Bergeron, Eduard Cerny, Alan Hunter, Andy Nightingale

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Loot Price R2,941 Discovery Miles 29 410 | Repayment Terms: R276 pm x 12*

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Offers users the first resource guide that combines both the methodology and basics of SystemVerilog Addresses how all these pieces fit together and how they should be used to verify complex chips rapidly and thoroughly. Unique in its broad coverage of SystemVerilog, advanced functional verification, and the combination of the two.

General

Imprint: Springer-Verlag New York
Country of origin: United States
Release date: December 2014
First published: 2006
Authors: Janick Bergeron • Eduard Cerny • Alan Hunter • Andy Nightingale
Dimensions: 235 x 155 x 27mm (L x W x T)
Format: Paperback
Pages: 503
Edition: 2006 ed.
ISBN-13: 978-1-4614-9813-1
Categories: Books > Professional & Technical > Technology: general issues > Technical design > Computer aided design (CAD)
Books > Professional & Technical > Energy technology & engineering > Electrical engineering > General
Books > Professional & Technical > Electronics & communications engineering > Electronics engineering > Circuits & components
Books > Computing & IT > Computer programming > Programming languages > General
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LSN: 1-4614-9813-9
Barcode: 9781461498131

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