Co-Design is the set of emerging techniques which allows for the simultaneous design of Hardware and Software. In many cases where the application is very demanding in terms of various performances (time, surface, power consumption), trade-offs between dedicated hardware and dedicated software are becoming increasingly difficult to decide upon in the early stages of a design. Verification techniques - such as simulation or proof techniques - that have proven necessary in the hardware design must be dramatically adapted to the simultaneous verification of Software and Hardware. Describing the latest tools available for both Co-Design and Co-Verification of systems, Hardware/Software Co-Design and Co-Verification offers a complete look at this evolving set of procedures for CAD environments. The book considers all trade-offs that have to be made when co-designing a system. Several models are presented for determining the optimum solution to any co-design problem, including partitioning, architecture synthesis and code generation. When deciding on trade-offs, one of the main factors to be considered is the flow of communication, especially to and from the outside world. This involves the modeling of communication protocols. An approach to the synthesis of interface circuits in the context of co-design is presented. Other chapters present a co-design oriented flexible component data-base and retrieval methods; a case study of an ethernet bridge, designed using LOTOS and co-design methodologies and finally a programmable user interface based on monitors. Hardware/Software Co-Design and Co-Verification will help designers and researchers to understand these latest techniques in system design and as such will be of interest to all involved in embedded system design.

Object-oriented techniques and languages have been proven to significantly increase engineering efficiency in software development. Many benefits are expected from their introduction into electronic modeling. Among them are better support for model reusability and flexibility, more efficient system modeling, and more possibilities in design space exploration and prototyping. Object-Oriented Modeling explores the latest techniques in object-oriented methods, formalisms and hardware description language extensions. The seven chapters comprising this book provide an overview of the latest object-oriented techniques for designing systems and hardware. Many examples are given in C++, VHDL and real-time programming languages. Object-Oriented Modeling describes further the use of object-oriented techniques in applications such as embedded systems, telecommunications and real-time systems, using the very latest techniques in object-oriented modeling. It is an essential guide to researchers, practitioners and students involved in software, hardware and system design.

From the reviews: "This book crystallizes what may become a defining moment in the electronics industry - the shift to platform-based design. It provides the first comprehensive guidebook for those who will build, and use, the integration platforms that may soon drive the system-on-chip revolution." Electronic Engineering Times

Models in system design follow the general tendency in electronics in terms of size, complexity and difficulty of maintenance. While a model should be a manageable representation of a system, this increasing complexity sometimes forces current CAD-tool designers and model writers to apply modeling techniques to the model itself. Model writers are interested in instrumenting their model, so as to extract critical information before the model is complete. CAD tools designers use internal representations of the design at various stages. The complexity has also led CAD-tool developers to develop formal tools, theories and methods to improve relevance, completeness and consistency of those internal representations. Information modeling involves the representation of objects, their properties and relationships. Performance Modeling When it comes to design choices and trade-offs, performance is generally the final key. However performance estimations have to be extracted at a very early stage in the system design. Performance modeling concerns the set of tools and techniques that allow or help the designer to capture metrics relating to future architectures. Performance modeling encompasses the whole system, including software modeling. It has a strong impact on all levels of design choices, from hardware/software partitioning to the final layout. Information Modeling Specification and formalism have in the past traditionally played little part in the design and development of EDA systems, their support environments, languages and processes. Instead, EDA system developers and EDA system users have seemed to be content to operate within environments that are often extremely complex and may be poorly tested and understood. This situation has now begun to change with the increasing use of techniques drawn from the domains of formal specification and database design. This section of this volume addresses aspects of the techniques being used. In particular, it considers a specific formalism, called information modeling, which has gained increasing acceptance recently and is now a key part of many of the proposals in the EDA Standards Roadmap, which promises to be of significance to the EDA industry. In addition, the section looks at an example of a design system from the point of view of its underlying understanding of the design process rather than through a consideration of particular CAD algorithms. Meta-Modeling: Performance and Information Modeling contains papers describing the very latest techniques used in meta-modeling. It will be a valuable text for researchers, practitioners and students involved in Electronic Design Automation.

ConieD is the biannual Congress on Computers in Education, organised by the Spanish Association for the Development of Computers in Education (ADIE). The last Congress, held in Puertollano (Ciudad Real), brought together researchers in different areas, ranging from web applications, educational environments, or Human-Computer Interaction to Artificial Intelligence in Education. The common leitmotiv of the major part of the lectures was the World Wide Web. In particular, the focus was on the real possibilities that this media presents in order to make the access of students to educational resources possible anywhere and anytime. This fact was highlighted in the Conclusions of the Congress following this Preface as the Introduction. From the full 92 papers presented to the Programme Committee we have selected the best 24 papers that we are presenting in this book. The selection of papers was a very difficult process, taking into account that the papers presented in the Congress (60) were all good enough to appear in this book. Only the restrictions of the extension of this book have limited the number of papers to 24. These papers represent the current high-quality contributions of Spanish research groups in Computers in Education. Manuel Ortega Cantero Jose Bravo Rodriguez Editors xiii Introduction ConieD'99 (1st National Congress on Computers in Education) has brought together a very important group of Spanish and Latin American researchers devoted to studying the application and use of computers in education."

SPSS Statistics: A Practical Guide gives students step-by-step guidance through the process of using SPSS software to analyse, interpret and report on data. This spiral bound text is concise yet detailed, and is praised for its friendly, practical, and visual pedagogical approach that focuses on ‘doing’.

The illustrated step-by-step examples work through each statistical procedure and are followed by interpretation and reporting of results in APA style.

The VITAL specification addresses the issues of interoperability, backannotation and high performance simulation for sign-off quality ASIC libraries in VHDL. VITAL provides modeling guidelines and a set of pre-defined packages (containing pre-defined routines for modeling functionality and timing) to facilitate the acceleration of designs which use cells from a VITAL library. The VITAL Level-I guidelines constrain the modeling capabilities provided by VHDL in order to facilitate higher performance (Figure I). Accumulating "gains" Constrained "flexibility" Higher performance & Increased capacity Benefits Flexibility FujI VHDL 1076 Figure 1: VHDL and VITAL Even within the Level-I guidelines, there are several ways in which a model can be written. In this chapter, we highlight the various modeling trade-offs and provide guidelines which can be used for developing efficient models. We will also discuss the techniques that can be used by tool developers to accelerate the simulation of VIT AL based designs. 2.2. OVERVIEW OF A VITAL LEVEL-l ARCIDTECTURE The VITAL specification is versatile enough to support several modeling styles e.g., distributed delay style, pin-to-pin delay style etc. In general, a VITAL Level-I model can have the structure illustrated in Figure 2."

Several aspects of informatics curricula and teaching methods at the university level are reported in this volume, including:
*Challenges in defining an international curriculum;
*The diversity in informatics curricula;
*Computing programs for scientists and engineers;
*Patterns of curriculum design;
*Student interaction;
*Teaching of programming;
*Peer review in education.

This book contains a selection of the papers presented at the Working Conference on Informatics Curricula, Teaching Methods and Best Practice (ICTEM 2002), which was sponsored by the International Federation for Information Processing (IFIP) Working Group 3.2, and held in Florian polis, Brazil in July 2002.

The working groups were organized in three parallel tracks. Working Group 1 discussed the "Directions and Challenges in Informatics Education." The focus of Working Group 2 was "Teaching Programming and Problem Solving." Working Group 3 discussed "Computing: The Shape of an Evolving Discipline." Each working group worked actively and prepared a report with the results of the discussions; these reports are included as the second part of this book.

Digital Timing Macromodeling for VLSI Design Verification first of all provides an extensive history of the development of simulation techniques. It presents detailed discussion of the various techniques implemented in circuit, timing, fast-timing, switch-level timing, switch-level, and gate-level simulation. It also discusses mixed-mode simulation and interconnection analysis methods. The review in Chapter 2 gives an understanding of the advantages and disadvantages of the many techniques applied in modern digital macromodels. The book also presents a wide variety of techniques for performing nonlinear macromodeling of digital MOS subcircuits which address a large number of shortcomings in existing digital MOS macromodels. Specifically, the techniques address the device model detail, transistor coupling capacitance, effective channel length modulation, series transistor reduction, effective transconductance, input terminal dependence, gate parasitic capacitance, the body effect, the impact of parasitic RC-interconnects, and the effect of transmission gates. The techniques address major sources of errors in existing macromodeling techniques, which must be addressed if macromodeling is to be accepted in commercial CAD tools by chip designers. The techniques presented in Chapters 4-6 can be implemented in other macromodels, and are demonstrated using the macromodel presented in Chapter 3. The new techniques are validated over an extremely wide range of operating conditions: much wider than has been presented for previous macromodels, thus demonstrating the wide range of applicability of these techniques.

SECIII-Social, Ethical and Cognitive Issues of Informatics and ICT Welcome to the post-conference book of SECIII, the IFIP Open Conference on Social, Ethical and Cognitive Issues of Informatics and ICT (Information and Communication Technology) which took place from July 22-26, 2002 at the University of Dortmund, Germany, in co-operation with the German computer society (Gesellschaft flir Informatik). Unlike most international conferences, those organised within the IFIP education community are active events. This wasn't a dry academic conference - teachers, lecturers and curriculum experts, policy makers, researchers and manufacturers mingled and worked together to explore, reflect and discuss social, ethical and cognitive issues. The added value lies in what they, the participants, took away in new ideas for future research and practice, and in the new networks that were formed, both virtual and real. In addition to Keynote Addresses and Paper Presentations from international authors, there were Provocative Paper sessions, Case Studies, Focussed Debates and Creative Exchange sessions as well as professional Working Groups who debated particular themes. The Focussed Debate sessions helped to stimulate the sense of engagement among conference participants. A Market Place with follow-up Working Groups was a positive highlight and galvanised participants to produce interesting reports. These were presented to the conference on its last day. Cross-fertilisation between the papers generated some surprising and useful cross-referencing and a plethora of social, ethical and cognitive issues emerged in the discussions that followed the paper presentations.

Modern electronics is driven by the explosive growth of digital communications and multi-media technology. A basic challenge is to design first-time-right complex digital systems, that meet stringent constraints on performance and power dissipation. In order to combine this growing system complexity with an increasingly short time-to-market, new system design technologies are emerging based on the paradigm of embedded programmable processors. This concept introduces modularity, flexibility and re-use in the electronic system design process. However, its success will critically depend on the availability of efficient and reliable CAD tools to design, programme and verify the functionality of embedded processors. Recently, new research efforts emerged on the edge between software compilation and hardware synthesis, to develop high-quality code generation tools for embedded processors. Code Generation for Embedded Systems provides a survey of these new developments. Although not limited to these targets, the main emphasis is on code generation for modern DSP processors. Important themes covered by the book include: the scope of general purpose versus application-specific processors, machine code quality for embedded applications, retargetability of the code generation process, machine description formalisms, and code generation methodologies. Code Generation for Embedded Systems is the essential introduction to this fast developing field of research for students, researchers, and practitioners alike.

Models in System Design tracks the general trend in electronics in terms of size, complexity and difficulty of maintenance. System design is by nature combined with prototyping, mixed domain design, and verification, and it is no surprise that today's modeling and models are used in various levels of system design and verification. In order to deal with constraints induced by volume and complexity, new methods and techniques have been defined. Models in System Design provides an overview of the latest modeling techniques for use by system designers. The first part of the book considers system level design, discussing such issues as abstraction, performance and trade-offs. There is also a section on automating system design. The second part of the book deals with some of the newest aspects of embedded system design. These include co-verification and prototyping. Finally, the book includes a section on the use of the MCSE methodology for hardware/software co-design. Models in System Design will help designers and researchers to understand these latest techniques in system design and as such will be of interest to all involved in embedded system design.

OmeGA: A Competent Genetic Algorithm for Solving Permutation and Scheduling Problems addresses two increasingly important areas in GA implementation and practice. OmeGA, or the ordering messy genetic algorithm, combines some of the latest in competent GA technology to solve scheduling and other permutation problems. Competent GAs are those designed for principled solutions of hard problems, quickly, reliably, and accurately. Permutation and scheduling problems are difficult combinatorial optimization problems with commercial import across a variety of industries.

This book approaches both subjects systematically and clearly. The first part of the book presents the clearest description of messy GAs written to date along with an innovative adaptation of the method to ordering problems. The second part of the book investigates the algorithm on boundedly difficult test functions, showing principled scale up as problems become harder and longer. Finally, the book applies the algorithm to a test function drawn from the literature of scheduling.

Circuit simulation has been a topic of great interest to the integrated circuit design community for many years. It is a difficult, and interesting, problem be cause circuit simulators are very heavily used, consuming thousands of computer hours every year, and therefore the algorithms must be very efficient. In addi tion, circuit simulators are heavily relied upon, with millions of dollars being gambled on their accuracy, and therefore the algorithms must be very robust. At the University of California, Berkeley, a great deal of research has been devoted to the study of both the numerical properties and the efficient imple mentation of circuit simulation algorithms. Research efforts have led to several programs, starting with CANCER in the 1960's and the enormously successful SPICE program in the early 1970's, to MOTIS-C, SPLICE, and RELAX in the late 1970's, and finally to SPLICE2 and RELAX2 in the 1980's. Our primary goal in writing this book was to present some of the results of our current research on the application of relaxation algorithms to circuit simu lation. As we began, we realized that a large body of mathematical and exper imental results had been amassed over the past twenty years by graduate students, professors, and industry researchers working on circuit simulation. It became a secondary goal to try to find an organization of this mass of material that was mathematically rigorous, had practical relevance, and still retained the natural intuitive simplicity of the circuit simulation subject."

AND BACKGROUND 1. 1 CAD, Specification and Simulation Computer Aided Design (CAD) is today a widely used expression referring to the study of ways in which computers can be used to expedite the design process. This can include the design of physical systems, architectural environments, manufacturing processes, and many other areas. This book concentrates on one area of CAD: the design of computer systems. Within this area, it focusses on just two aspects of computer design, the specification and the simulation of digital systems. VLSI design requires support in many other CAD areas, induding automatic layout. IC fabrication analysis, test generation, and others. The problem of specification is unique, however, in that it i > often the first one encountered in large chip designs, and one that is unlikely ever to be completely automated. This is true because until a design's objectives are specified in a machine-readable form, there is no way for other CAD tools to verify that the target system meets them. And unless the specifications can be simulated, it is unlikely that designers will have confidence in them, since specifications are potentially erroneous themselves. (In this context the term target system refers to the hardware and/or software that will ultimately be fabricated. ) On the other hand, since the functionality of a VLSI chip is ultimately determined by its layout geometry, one might question the need for CAD tools that work with areas other than layout.

Memory Issues in Embedded Systems-On-Chip: Optimizations and Explorations is designed for different groups in the embedded systems-on-chip arena. First, it is designed for researchers and graduate students who wish to understand the research issues involved in memory system optimization and exploration for embedded systems-on-chip. Second, it is intended for designers of embedded systems who are migrating from a traditional micro-controllers centered, board-based design methodology to newer design methodologies using IP blocks for processor-core-based embedded systems-on-chip. Also, since Memory Issues in Embedded Systems-on-Chip: Optimization and Explorations illustrates a methodology for optimizing and exploring the memory configuration of embedded systems-on-chip, it is intended for managers and system designers who may be interested in the emerging capabilities of embedded systems-on-chip design methodologies for memory-intensive applications.

Life in the last quarter of the twentieth century presents a baffling array of complex issues. The benefits of technology are arrayed against the risks and hazards of those same technological marvels (frequently, though not always, arising as side effects or by-products). This confrontation poses very difficult choices for individuals as well as for those charged with making public policy. Some of the most challenging of these issues result because of the ability of technological innovation and deployment to outpace the capacity of institutions to assess and evaluate implications. In many areas, the rate of technological advance has now far outstripped the capabilities of institutional monitoring and control. While there are many instances in which technological advance occurs without adverse consequences (and in fact, yields tremendous benefits), frequently the advent of a major innovation brings a wide array of unforeseen and (to some) undesirable effects. This problem is exacerbated as the interval between the initial development of a technology and its deployment is shortened, since the opportunity for cautious appraisal is decreased.

Very large scale integration (VLSI) technologies are now maturing with a current emphasis toward submicron structures and sophisticated applications combining digital as well as analog circuits on a single chip. Abundant examples are found on today's advanced systems for telecom munications, robotics, automotive electronics, image processing, intelli gent sensors, etc .. Exciting new applications are being unveiled in the field of neural computing where the massive use of analog/digital VLSI technologies will have a significant impact. To match such a fast technological trend towards single chip ana logi digital VLSI systems, researchers worldwide have long realized the vital need of producing advanced computer aided tools for designing both digital and analog circuits and systems for silicon integration. Ar chitecture and circuit compilation, device sizing and the layout genera tion are but a few familiar tasks on the world of digital integrated circuit design which can be efficiently accomplished by matured computer aided tools. In contrast, the art of tools for designing and producing analog or even analogi digital integrated circuits is quite primitive and still lack ing the industrial penetration and acceptance already achieved by digital counterparts. In fact, analog design is commonly perceived to be one of the most knowledge-intensive design tasks and analog circuits are still designed, largely by hand, by expert intimately familiar with nuances of the target application and integrated circuit fabrication process. The techniques needed to build good analog circuits seem to exist solely as expertise invested in individual designers."

This book proposes a new approach to circuit simulation that is still in its infancy. The reason for publishing this work as a monograph at this time is to quickly distribute these ideas to the research community for further study. The book is based on a doctoral dissertation undertaken at MIT between 1982 and 1985. In 1982 the author joined a research group that was applying bounding techniques to simple VLSI timing analysis models. The conviction that bounding analysis could also be successfully applied to sophisticated digital MOS circuit models led to the research presented here. Acknowledgments 'me author would like to acknowledge many helpful discussions and much support from his research group at MIT, including Lance Glasser, John Wyatt, Jr., and Paul Penfield, Jr. Many others have also contributed to this work in some way, including Albert Ruchli, Mark Horowitz, Rich Zippel, Chtis Terman, Jacob White, Mark Matson, Bob Armstrong, Steve McCormick, Cyrus Bamji, John Wroclawski, Omar Wing, Gary Dare, Paul Bassett, and Rick LaMaire. The author would like to give special thanks to his wife, Deborra, for her support and many contributions to the presentation of this research. The author would also like to thank his parents for their encouragement, and IBM for its financial support of t, I-Jis project through a graduate fellowship. THE BOUNDING APPROACH TO VLSI CIRCUIT SIMULATION 1. INTRODUCTION The VLSI revolution of the 1970's has created a need for new circuit analysis techniques.