This book provides readers with an insightful guide to the design, testing and optimization of 2.5D integrated circuits. The authors describe a set of design-for-test methods to address various challenges posed by the new generation of 2.5D ICs, including pre-bond testing of the silicon interposer, at-speed interconnect testing, built-in self-test architecture, extest scheduling, and a programmable method for low-power scan shift in SoC dies. This book covers many testing techniques that have already been used in mainstream semiconductor companies. Readers will benefit from an in-depth look at test-technology solutions that are needed to make 2.5D ICs a reality and commercially viable.

The three-volume set LNCS 10860, 10861 and 10862 constitutes the proceedings of the 18th International Conference on Computational Science, ICCS 2018, held in Wuxi, China, in June 2018. The total of 155 full and 66 short papers presented in this book set was carefully reviewed and selected from 404 submissions. The papers were organized in topical sections named: Part I: ICCS Main Track Part II: Track of Advances in High-Performance Computational Earth Sciences: Applications and Frameworks; Track of Agent-Based Simulations, Adaptive Algorithms and Solvers; Track of Applications of Matrix Methods in Artificial Intelligence and Machine Learning; Track of Architecture, Languages, Compilation and Hardware Support for Emerging ManYcore Systems; Track of Biomedical and Bioinformatics Challenges for Computer Science; Track of Computational Finance and Business Intelligence; Track of Computational Optimization, Modelling and Simulation; Track of Data, Modeling, and Computation in IoT and Smart Systems; Track of Data-Driven Computational Sciences; Track of Mathematical-Methods-and-Algorithms for Extreme Scale; Track of Multiscale Modelling and Simulation Part III: Track of Simulations of Flow and Transport: Modeling, Algorithms and Computation; Track of Solving Problems with Uncertainties; Track of Teaching Computational Science; Poster Papers

This book provides a comprehensive introduction to hardware security, from specification to implementation. Applications discussed include embedded systems ranging from small RFID tags to satellites orbiting the earth. The authors describe a design and synthesis flow, which will transform a given circuit into a secure design incorporating counter-measures against fault attacks. In order to address the conflict between testability and security, the authors describe innovative design-for-testability (DFT) computer-aided design (CAD) tools that support security challenges, engineered for compliance with existing, commercial tools. Secure protocols are discussed, which protect access to necessary test infrastructures and enable the design of secure access controllers.

This book describes novel software concepts to increase reliability under user-defined constraints. The authors' approach bridges, for the first time, the reliability gap between hardware and software. Readers will learn how to achieve increased soft error resilience on unreliable hardware, while exploiting the inherent error masking characteristics and error (stemming from soft errors, aging, and process variations) mitigations potential at different software layers.

This thesis introduces novel and significant results regarding the analysis and synthesis of positive systems, especially under l1 and L1 performance. It describes stability analysis, controller synthesis, and bounding positivity-preserving observer and filtering design for a variety of both discrete and continuous positive systems. It subsequently derives computationally efficient solutions based on linear programming in terms of matrix inequalities, as well as a number of analytical solutions obtained for special cases. The thesis applies a range of novel approaches and fundamental techniques to the further study of positive systems, thus contributing significantly to the theory of positive systems, a "hot topic" in the field of control.

This book discusses the design and performance analysis of SDRAM controllers that cater to both real-time and best-effort applications, i.e. mixed-time-criticality memory controllers. The authors describe the state of the art, and then focus on an architecture template for reconfigurable memory controllers that addresses effectively the quickly evolving set of SDRAM standards, in terms of worst-case timing and power analysis, as well as implementation. A prototype implementation of the controller in SystemC and synthesizable VHDL for an FPGA development board are used as a proof of concept of the architecture template.

This book makes powerful Field Programmable Gate Array (FPGA) and reconfigurable technology accessible to software engineers by covering different state-of-the-art high-level synthesis approaches (e.g., OpenCL and several C-to-gates compilers). It introduces FPGA technology, its programming model, and how various applications can be implemented on FPGAs without going through low-level hardware design phases. Readers will get a realistic sense for problems that are suited for FPGAs and how to implement them from a software designer's point of view. The authors demonstrate that FPGAs and their programming model reflect the needs of stream processing problems much better than traditional CPU or GPU architectures, making them well-suited for a wide variety of systems, from embedded systems performing sensor processing to large setups for Big Data number crunching. This book serves as an invaluable tool for software designers and FPGA design engineers who are interested in high design productivity through behavioural synthesis, domain-specific compilation, and FPGA overlays. Introduces FPGA technology to software developers by giving an overview of FPGA programming models and design tools, as well as various application examples; Provides a holistic analysis of the topic and enables developers to tackle the architectural needs for Big Data processing with FPGAs; Explains the reasons for the energy efficiency and performance benefits of FPGA processing; Provides a user-oriented approach and a sense for where and how to apply FPGA technology.

This comprehensive textbook on the field programmable gate array (FPGA) covers its history, fundamental knowledge, architectures, device technologies, computer-aided design technologies, design tools, examples of application, and future trends. Programmable logic devices represented by FPGAs have been rapidly developed in recent years and have become key electronic devices used in most IT products. This book provides both complete introductions suitable for students and beginners, and high-level techniques useful for engineers and researchers in this field. Differently developed from usual integrated circuits, the FPGA has unique structures, design methodologies, and application techniques. Allowing programming by users, the device can dramatically reduce the rising cost of development in advanced semiconductor chips. The FPGA is now driving the most advanced semiconductor processes and is an all-in-one platform combining memory, CPUs, and various peripheral interfaces. This book introduces the FPGA from various aspects for readers of different levels. Novice learners can acquire a fundamental knowledge of the FPGA, including its history, from Chapter 1; the first half of Chapter 2; and Chapter 4. Professionals who are already familiar with the device will gain a deeper understanding of the structures and design methodologies from Chapters 3 and 5. Chapters 6-8 also provide advanced techniques and cutting-edge applications and trends useful for professionals. Although the first parts are mainly suitable for students, the advanced sections of the book will be valuable for professionals in acquiring an in-depth understanding of the FPGA to maximize the performance of the device.

Originally developed to support video games, graphics processor units (GPUs) are now increasingly used for general-purpose (non-graphics) applications ranging from machine learning to mining of cryptographic currencies. GPUs can achieve improved performance and efficiency versus central processing units (CPUs) by dedicating a larger fraction of hardware resources to computation. In addition, their general-purpose programmability makes contemporary GPUs appealing to software developers in comparison to domain-specific accelerators. This book provides an introduction to those interested in studying the architecture of GPUs that support general-purpose computing. It collects together information currently only found among a wide range of disparate sources. The authors led development of the GPGPU-Sim simulator widely used in academic research on GPU architectures. The first chapter of this book describes the basic hardware structure of GPUs and provides a brief overview of their history. Chapter 2 provides a summary of GPU programming models relevant to the rest of the book. Chapter 3 explores the architecture of GPU compute cores. Chapter 4 explores the architecture of the GPU memory system. After describing the architecture of existing systems, Chapters 3 and 4 provide an overview of related research. Chapter 5 summarizes cross-cutting research impacting both the compute core and memory system. This book should provide a valuable resource for those wishing to understand the architecture of graphics processor units (GPUs) used for acceleration of general-purpose applications and to those who want to obtain an introduction to the rapidly growing body of research exploring how to improve the architecture of these GPUs.

This book describes state-of-the-art techniques for designing real-time computer systems. The author shows how to estimate precisely the effect of cache architecture on the execution time of a program, how to dispatch workload on multicore processors to optimize resources, while meeting deadline constraints, and how to use closed-form mathematical approaches to characterize highly variable workloads and their interaction in a networked environment. Readers will learn how to deal with unpredictable timing behaviors of computer systems on different levels of system granularity and abstraction.

This unique text/reference provides a comprehensive review of distributed simulation (DS) from the perspective of Model Driven Engineering (MDE), illustrating how MDE affects the overall lifecycle of the simulation development process. Numerous practical case studies are included to demonstrate the utility and applicability of the methodology, many of which are developed from tools available to download from the public domain. Topics and features: Provides a thorough introduction to the fundamental concepts, principles and processes of modeling and simulation, MDE and high-level architecture Describes a road map for building a DS system in accordance with the MDE perspective, and a technical framework for the development of conceptual models Presents a focus on federate (simulation environment) architectures, detailing a practical approach to the design of federations (i.e., simulation member design) Discusses the main activities related to scenario management in DS, and explores the process of MDE-based implementation, integration and testing Reviews approaches to simulation evolution and modernization, including architecture-driven modernization for simulation modernization Examines the potential synergies between the agent, DS, and MDE methodologies, suggesting avenues for future research at the intersection of these three fields Distributed Simulation - A Model Driven Engineering Approach is an important resource for all researchers and practitioners involved in modeling and simulation, and software engineering, who may be interested in adopting MDE principles when developing complex DS systems.

This book discusses the digital design of integrated circuits under process variations, with a focus on design-time solutions. The authors describe a step-by-step methodology, going from logic gates to logic paths to the circuit level. Topics are presented in comprehensively, without overwhelming use of analytical formulations. Emphasis is placed on providing digital designers with understanding of the sources of process variations, their impact on circuit performance and tools for improving their designs to comply with product specifications. Various circuit-level "design hints" are highlighted, so that readers can use then to improve their designs. A special treatment is devoted to unique design issues and the impact of process variations on the performance of FinFET based circuits. This book enables readers to make optimal decisions at design time, toward more efficient circuits, with better yield and higher reliability.

This book provides a hands-on, application-oriented guide to the language and methodology of both SystemVerilog Assertions and SystemVerilog Functional Coverage. Readers will benefit from the step-by-step approach to functional hardware verification using SystemVerilog Assertions and Functional Coverage, which will enable them to uncover hidden and hard to find bugs, point directly to the source of the bug, provide for a clean and easy way to model complex timing checks and objectively answer the question 'have we functionally verified everything'. Written by a professional end-user of ASIC/SoC/CPU and FPGA design and Verification, this book explains each concept with easy to understand examples, simulation logs and applications derived from real projects. Readers will be empowered to tackle the modeling of complex checkers for functional verification, thereby drastically reducing their time to design and debug. This updated second edition addresses the latest functional set released in IEEE-1800 (2012) LRM, including numerous additional operators and features. Additionally, many of the Concurrent Assertions/Operators explanations are enhanced, with the addition of more examples and figures. * Covers in its entirety the latest IEEE-1800 2012 LRM syntax and semantics; * Covers both SystemVerilog Assertions and SystemVerilog Functional Coverage language and methodologies; * Provides practical examples of the what, how and why of Assertion Based Verification and Functional Coverage methodologies; * Explains each concept in a step-by-step fashion and applies it to a practical real life example; * Includes 6 practical LABs that enable readers to put in practice the concepts explained in the book.

This book-presents new methods and tools for the integration and simulation of smart devices. The design approach described in this book explicitly accounts for integration of Smart Systems components and subsystems as a specific constraint. It includes methodologies and EDA tools to enable multi-disciplinary and multi-scale modeling and design, simulation of multi-domain systems, subsystems and components at all levels of abstraction, system integration and exploration for optimization of functional and non-functional metrics. By covering theoretical and practical aspects of smart device design, this book targets people who are working and studying on hardware/software modelling, component integration and simulation under different positions (system integrators, designers, developers, researchers, teachers, students etc.). In particular, it is a good introduction to people who have interest in managing heterogeneous components in an efficient and effective way on different domains and different abstraction levels. People active in smart device development can understand both the current status of practice and future research directions. * Provides a comprehensive overview of smart systems design, focusing on design challenges and cutting-edge solutions; * Enables development of a co-simulation and co-design environment that accounts for the peculiarities of the basic subsystems and components to be integrated; * Describes development of modeling and design techniques, methods and tools that enable multi-domain simulation and optimization at various levels of abstraction and across different technological domains.

This book constitutes the refereed proceedings of the 9th International Workshop on Post-Quantum Cryptography, PQCrypto 2018, held in Fort Lauderdale, FL, USA, in April 2018. The 24 revised full papers presented were carefully reviewed and selected from 97 submissions. The papers are organized in topical sections on Code-based Cryptography; Cryptanalysis; Hash-based Cryptography; Isogenies in Cryptography; Lattice-based Cryptography; Multivariate Cryptography; Protocols; Quantum Algorithms.

This book constitutes the proceedings of the 14th International Conference on Applied Reconfigurable Computing, ARC 2018, held in Santorini, Greece, in May 2018. The 29 full papers and 22 short presented in this volume were carefully reviewed and selected from 78 submissions. In addition, the volume contains 9 contributions from research projects. The papers were organized in topical sections named: machine learning and neural networks; FPGA-based design and CGRA optimizations; applications and surveys; fault-tolerance, security and communication architectures; reconfigurable and adaptive architectures; design methods and fast prototyping; FPGA-based design and applications; and special session: research projects.

The Virtual and the Real in Planning and Urban Design: Perspectives, Practices and Applicationsexplores the merging relationship between physical and virtual spaces in planning and urban design. Technological advances such as smart sensors, interactive screens, locative media and evolving computation software have impacted the ways in which people experience, explore, interact with and create these complex spaces. This book draws together a broad range of interdisciplinary researchers in areas such as architecture, urban design, spatial planning, geoinformation science, computer science and psychology to introduce the theories, models, opportunities and uncertainties involved in the interplay between virtual and physical spaces. Using a wide range of international contributors, from the UK, USA, Germany, France, Switzerland, Netherlands and Japan, it provides a framework for assessing how new technology alters our perception of physical space.

A hands-on guide to writing a Message Passing Interface, this book takes the reader on a tour across major MPI implementations, best optimization techniques, application relevant usage hints, and a historical retrospective of the MPI world, all based on a quarter of a century spent inside MPI. Readers will learn to write MPI implementations from scratch, and to design and optimize communication mechanisms using pragmatic subsetting as the guiding principle. Inside the Message Passing Interface also covers MPI quirks and tricks to achieve best performance. Dr. Alexander Supalov created the Intel Cluster Tools product line, including the Intel MP Library that he designed and led between 2003 and 2015. He invented the common MPICH ABI and also guided Intel efforts in the MPI Forum during the development of the MPI-2.1, MPI-2.2, and MPI-3 standards. Before that, Alexander designed new finite-element mesh-generation methods, contributing to the PARMACS and PARASOL interfaces, and developed the first full MPI-2 and IMPI implementations in the world. He graduated from the Moscow Institute of Physics and Technology in 1990, and earned his PhD in applied mathematics at the Institute of Numerical Mathematics of the Russian Academy of Sciences in 1995. Alexander holds 26 patents (more pending worldwide).

This book constitutes the refereed proceedings of the 21st CCF Conference on Computer Engineering and Technology, NCCET 2017, held in Xiamen, China, in August 2017. The 13 full papers presented were carefully reviewed and selected from 108 submissions. They address topics such as processor architecture; application specific processors; computer application and software optimization; technology on the horizon.

This book describes algorithmic methods and parallelization techniques to design a parallel sparse direct solver which is specifically targeted at integrated circuit simulation problems. The authors describe a complete flow and detailed parallel algorithms of the sparse direct solver. They also show how to improve the performance by simple but effective numerical techniques. The sparse direct solver techniques described can be applied to any SPICE-like integrated circuit simulator and have been proven to be high-performance in actual circuit simulation. Readers will benefit from the state-of-the-art parallel integrated circuit simulation techniques described in this book, especially the latest parallel sparse matrix solution techniques.

Learn how to institute and implement enterprise architecture in your organisation. You can make a quick start and establish a baseline for your enterprise architecture within ten weeks, then grow and stabilise the architecture over time using the proven Ready, Set, Go Approach. Reading this book will: Give you directions on how to institute and implement enterprise architecture in your organization. You will be able to build close relationships with stakeholders and delivery teams, but you will not need to micromanage the architectures operations; Increase your awareness that enterprise architecture is about business, not information technology; Enable you to initiate and facilitate dramatic business development. The architecture of an enterprise must be tolerant of currently unknown business initiatives; Show you how to get a holistic view of the process of implementing enterprise architecture; Make you aware that information is a key business asset and that information architecture is a key part of the enterprise architecture; Allow you to learn from our experiences. This book is based on our 30 years of work in the enterprise architecture field, colleagues in Europe, customer cases, and students. If your company is about to make a major change and you are looking for a way to reduce the changes into manageable pieces -- and still retain control of how they fit together -- this is your handbook. Maybe you are already acting as an enterprise architect and using a formal method, but you need practical hints. Or maybe you are about to set up an enterprise architect network or group of specialists and need input on how to organise your work. The Ready-Set-Go method for introducing enterprise architecture provides you, the enterprise architect, with an immediate understanding of the basic steps for starting, organising, and operating the entirety of your organisations architecture. Chapter 1 shows how to model and analyse your business operations, assess their current status, construct a future scenario, compare it to the current structure, analyse what you see, and show the result in a city plan. Chapter 2 deals with preparing for the implementation of the architecture with governance, enterprise architecture organisation, staffing, etc. This is the organising step before beginning the actual work. Chapter 3 establishes how to implement a city plan in practice. It deals with the practicalities of working as an enterprise architect and is called the running step. The common thread through all aspects of the enterprise architects work is the architects mastery of a number of tools, such as business models, process models, information models, and matrices. We address how to initiate the architecture process within the organisation in such a way that the overarching enterprise architecture and architecture-driven approach can be applied methodically and gradually improved.

In Synthetic Vision: Using Volume Learning and Visual DNA, a holistic model of the human visual system is developed into a working model in C++, informed by the latest neuroscience, DNN, and computer vision research. The author's synthetic visual pathway model includes the eye, LGN, visual cortex, and the high level PFC learning centers. The corresponding visual genome model (VGM), begun in 2014, is introduced herein as the basis for a visual genome project analogous to the Human Genome Project funded by the US government. The VGM introduces volume learning principles and Visual DNA (VDNA) taking a multivariate approach beyond deep neural networks. Volume learning is modeled as programmable learning and reasoning agents, providing rich methods for structured agent classification networks. Volume learning incorporates a massive volume of multivariate features in various data space projections, collected into strands of Visual DNA, analogous to human DNA genes. VGM lays a foundation for a visual genome project to sequence VDNA as visual genomes in a public database, using collaborative research to move synthetic vision science forward and enable new applications. Bibliographical references are provided to key neuroscience, computer vision, and deep learning research, which form the basis for the biologically plausible VGM model and the synthetic visual pathway. The book also includes graphical illustrations and C++ API reference materials to enable VGM application programming. Open source code licenses are available for engineers and scientists. Scott Krig founded Krig Research to provide some of the world's first vision and imaging systems worldwide for military, industry, government, and academic use. Krig has worked for major corporations and startups in the areas of machine learning, computer vision, imaging, graphics, robotics and automation, computer security and cryptography. He has authored international patents in the areas of computer architecture, communications, computer security, digital imaging, and computer vision, and studied at Stanford. Scott Krig is the author of the English/Chinese Springer book Computer Vision Metrics, Survey, Taxonomy and Analysis of Computer Vision, Visual Neuroscience, and Deep Learning, Textbook Edition, as well as other books, articles, and papers.

An expert guide to understanding and making optimum use of BSIM

Used by more chip designers worldwide than any other comparable model, the Berkeley Short-Channel IGFET Model (BSIM) has, over the past few years, established itself as the de facto standard MOSFET SPICE model for circuit simulation and CMOS technology development. Yet, until now, there have been no independent expert guides or tutorials to supplement the various BSIM manuals currently available. Written by a noted expert in the field, this book fills that gap in the literature by providing a comprehensive guide to understanding and making optimal use of BSIM3 and BSIM4.

Drawing upon his extensive experience designing with BSIM, William Liu provides a brief history of the model, discusses the various advantages of BSIM over other models, and explores the reasons why BSIM3 has been adopted by the majority of circuit manufacturers. He then provides engineers with the detailed practical information and guidance they need to master all of BSIM’s features. He:

• Summarizes key BSIM3 components
• Represents the BSIM3 model with equivalent circuits for various operating conditions
• Provides a comprehensive glossary of modeling terminology
• Lists alphabetically BSIM3 parameters along with their meanings and relevant equations
• Explores BSIM3’s flaws and provides improvement suggestions
• Describes all of BSIM4’s improvements and new features

This book constitutes the refereed proceedings papers from the 8th International Workshop on Performance Modeling, Benchmarking and Simulation of High Performance Computing Systems, PMBS 2017, held in Denver, Colorado, USA, in November 2017. The 10 full papers and 3 short papers included in this volume were carefully reviewed and selected from 36 submissions. They were organized in topical sections named: performance evaluation and analysis; performance modeling and simulation; and short papers.

Model checking is one of the most successful verification techniques and has been widely adopted in traditional computing and communication hardware and software industries. This book provides the first systematic introduction to model checking techniques applicable to quantum systems, with broad potential applications in the emerging industry of quantum computing and quantum communication as well as quantum physics. Suitable for use as a course textbook and for self-study, graduate and senior undergraduate students will appreciate the step-by-step explanations and the exercises included. Researchers and engineers in the related fields can further develop these techniques in their own work, with the final chapter outlining potential future applications.