This book addresses challenges faced by both the algorithm designer and the chip designer, who need to deal with the ongoing increase of algorithmic complexity and required data throughput for today's mobile applications. The focus is on implementation aspects and implementation constraints of individual components that are needed in transceivers for current standards, such as UMTS, LTE, WiMAX and DVB-S2. The application domain is the so called outer receiver, which comprises the channel coding, interleaving stages, modulator, and multiple antenna transmission. Throughout the book, the focus is on advanced algorithms that are actually in use in modern communications systems. Their basic principles are always derived with a focus on the resulting communications and implementation performance. As a result, this book serves as a valuable reference for two, typically disparate audiences in communication systems and hardware design.

This book describes an approach for designing Systems-on-Chip such that the system meets precise mathematical requirements. The methodologies presented enable embedded systems designers to reuse intellectual property (IP) blocks from existing designs in an efficient, reliable manner, automatically generating correct SoCs from multiple, possibly mismatching, components.

This book provides a comprehensive guide to the design of sustainable and green computing systems (GSC). Coverage includes important breakthroughs in various aspects of GSC, including multi-core architectures, interconnection technology, data centers, high performance computing (HPC), and sensor networks. The authors address the challenges of power efficiency and sustainability in various contexts, including system design, computer architecture, programming languages, compilers and networking.

Building Your Next Big Thing with Google Cloud Platform shows you how to take advantage of the Google Cloud Platform technologies to build all kinds of cloud-hosted software and services for both public and private consumption. Whether you need a simple virtual server to run your legacy application or you need to architect a sophisticated high-traffic web application, Cloud Platform provides all the tools and products required to create innovative applications and a robust infrastructure to manage them. Google is known for the scalability, reliability, and efficiency of its various online products, from Google Search to Gmail. And, the results are impressive. Google Search, for example, returns results literally within fractions of second. How is this possible? Google custom-builds both hardware and software, including servers, switches, networks, data centers, the operating system's stack, application frameworks, applications, and APIs. Have you ever imagined what you could build if you were able to tap the same infrastructure that Google uses to create and manage its products? Now you can! Building Your Next Big Thing with Google Cloud Platform shows you how to take advantage of the Google Cloud Platform technologies to build all kinds of cloud-hosted software and services for both public and private consumption. Whether you need a simple virtual server to run your legacy application or you need to architect a sophisticated high-traffic web application, Cloud Platform provides all the tools and products required to create innovative applications and a robust infrastructure to manage them. Using this book as your compass, you can navigate your way through the Google Cloud Platform and turn your ideas into reality. The authors, both Google Developer Experts in Google Cloud Platform, systematically introduce various Cloud Platform products one at a time and discuss their strengths and scenarios where they are a suitable fit. But rather than a manual-like "tell all" approach, the emphasis is on how to Get Things Done so that you get up to speed with Google Cloud Platform as quickly as possible. You will learn how to use the following technologies, among others: Google Compute Engine Google App Engine Google Container Engine Google App Engine Managed VMs Google Cloud SQL Google Cloud Storage Google Cloud Datastore Google BigQuery Google Cloud Dataflow Google Cloud DNS Google Cloud Pub/Sub Google Cloud Endpoints Google Cloud Deployment Manager Author on Google Cloud Platform Google APIs and Translate API Using real-world examples, the authors first walk you through the basics of cloud computing, cloud terminologies and public cloud services. Then they dive right into Google Cloud Platform and how you can use it to tackle your challenges, build new products, analyze big data, and much more. Whether you're an independent developer, startup, or Fortune 500 company, you have never had easier to access to world-class production, product development, and infrastructure tools. Google Cloud Platform is your ticket to leveraging your skills and knowledge into making reliable, scalable, and efficient products-just like how Google builds its own products.

This four volume set of books constitutes the proceedings of the 36th International Conference Information Systems Architecture and Technology 2015, or ISAT 2015 for short, held on September 20-22, 2015 in Karpacz, Poland. The conference was organized by the Computer Science and Management Systems Departments, Faculty of Computer Science and Management, Wroclaw University of Technology, Poland. The papers included in the proceedings have been subject to a thorough review process by highly qualified peer reviewers. The accepted papers have been grouped into four parts: Part I-addressing topics including, but not limited to, systems analysis and modeling, methods for managing complex planning environment and insights from Big Data research projects. Part II-discoursing about topics including, but not limited to, Web systems, computer networks, distributed computing, and multi-agent systems and Internet of Things. Part III-discussing topics including, but not limited to, mobile and Service Oriented Architecture systems, high performance computing, cloud computing, knowledge discovery, data mining and knowledge based management. Part IV-dealing with topics including, but not limited to, finance, logistics and market problems, and artificial intelligence methods.

This four volume set of books constitutes the proceedings of the 36th International Conference Information Systems Architecture and Technology 2015, or ISAT 2015 for short, held on September 20-22, 2015 in Karpacz, Poland. The conference was organized by the Computer Science and Management Systems Departments, Faculty of Computer Science and Management, Wroclaw University of Technology, Poland. The papers included in the proceedings have been subject to a thorough review process by highly qualified peer reviewers. The accepted papers have been grouped into four parts: Part I-addressing topics including, but not limited to, systems analysis and modeling, methods for managing complex planning environment and insights from Big Data research projects. Part II-discoursing about topics including, but not limited to, Web systems, computer networks, distributed computing, and multi-agent systems and Internet of Things. Part III-discussing topics including, but not limited to, mobile and Service Oriented Architecture systems, high performance computing, cloud computing, knowledge discovery, data mining and knowledge based management. Part IV-dealing with topics including, but not limited to, finance, logistics and market problems, and artificial intelligence methods.

This book constitutes the refereed proceedings of the 18th National Conference on Computer Engineering and Technology, NCCET 2014, held in Guiyang, China, during July/August 2014. The 18 papers presented were carefully reviewed and selected from 85 submissions. They are organized in topical sections on processor architecture; computer application and software optimization; technology on the horizon.

Traditionally, design space exploration for Systems-on-Chip (SoCs) has focused on the computational aspects of the problem at hand. However, as the number of components on a single chip and their performance continue to increase, the communication architecture plays a major role in the area, performance and energy consumption of the overall system. As a result, a shift from computation-based to communication-based design becomes mandatory. Towards this end, network-on-chip (NoC) communication architectures have emerged recently as a promising alternative to classical bus and point-to-point communication architectures. In this dissertation, we study outstanding research problems related to modeling, analysis and optimization of NoC communication architectures. More precisely, we present novel design methodologies, software tools and FPGA prototypes to aid the design of application-specific NoCs.

This book describes model-based development of adaptive embedded systems, which enable improved functionality using the same resources. The techniques presented facilitate design from a higher level of abstraction, focusing on the problem domain rather than on the solution domain, thereby increasing development efficiency. Models are used to capture system specifications and to implement (manually or automatically) system functionality. The authors demonstrate the real impact of adaptivity on engineering of embedded systems by providing several industrial examples of the models used in the development of adaptive embedded systems.

Shortest Path Bridging is the most recent of this series of evolutionary steps, and is arguably one of the 3 or 4 most significant enhancements in Ethernet's history. Until SPB, Ethernet had retained its original control mechanisms, and these are now distinctly behind the state of the art in their properties. SPB refreshes this component of Ethernet, by taking the existing data path technology practically unaltered, and marrying it to a significant extension of the state of the art in distributed control planes, link state routing.

The book both explains both the "what" and the "why" of the standard. The intent is to provide a sense of the relative simplicity of 802.1aq, in terms of the small number of moving parts required to achieve what it does, and why those choices were made. It goes into what were elective decisions and what decisions were dictated by the design goals. It does this by using a multipart approach to the book. The first is a "what it is" description, intended to provide an overview of SPB. The second is separated out, and uses a narrative form to describe the design process and decisions that led to SPB, in order to provide further context in understanding the first part. The book is rounded out with applications and potential futures for the technology to suggest where it could go.

This book addresses dynamic modelling methodology and analyses of tree-type robotic systems. Such analyses are required to visualize the motion of a system without really building it. The book contains novel treatment of the tree-type systems using concept of kinematic modules and the corresponding Decoupled Natural Orthogonal Complements (DeNOC), unified representation of the multiple-degrees-of freedom-joints, efficient recursive dynamics algorithms, and detailed dynamic analyses of several legged robots. The book will help graduate students, researchers and practicing engineers in applying their knowledge of dynamics for analysis of complex robotic systems. The knowledge contained in the book will help one in virtual testing of robot operation, trajectory planning and control.

This book presents the methodologies and for embedded systems design, using field programmable gate array (FPGA) devices, for the most modern applications. Coverage includes state-of-the-art research from academia and industry on a wide range of topics, including applications, advanced electronic design automation (EDA), novel system architectures, embedded processors, arithmetic, and dynamic reconfiguration.

This book describes the emerging field of self-organizing, multicore, distributed and real-time embedded systems. Self -organization of both hardware and software can be a key technique to handle the growing complexity of modern computing systems. Distributed systems running hundreds of tasks on dozens of processors, each equipped with multiple cores, requires self-organization principles to ensure efficient and reliable operation. This book addresses various, so-called Self-X features such as self-configuration, self-optimization, self-adaptation, self-healing and self-protection.

This book serves a dual purpose: firstly to combine the treatment of circuits and digital electronics, and secondly, to establish a strong connection with the contemporary world of digital systems. The need for this approach arises from the observation that introducing digital electronics through a course in traditional circuit analysis is fast becoming obsolete. Our world has gone digital. Automata theory helps with the design of digital circuits such as parts of computers, telephone systems and control systems. A complete perspective is emphasized, because even the most elegant computer architecture will not function without adequate supporting circuits. The focus is on explaining the real-world implementation of complete digital systems. In doing so, the reader is prepared to immediately begin design and implementation work. This work serves as a bridge to take readers from the theoretical world to the everyday design world where solutions must be complete to be successful.

This textbook serves as an introduction to the subject of embedded systems design, with emphasis on integration of custom hardware components with software. The key problem addressed in the book is the following: how can an embedded systems designer strike a balance between flexibility and efficiency? The book describes how combining hardware design with software design leads to a solution to this important computer engineering problem. The book covers four topics in hardware/software codesign: fundamentals, the design space of custom architectures, the hardware/software interface and application examples. The book comes with an associated design environment that helps the reader to perform experiments in hardware/software codesign. Each chapter also includes exercises and further reading suggestions. Improvements in this second edition include labs and examples using modern FPGA environments from Xilinx and Altera, which will make the material in this book applicable to a greater number of courses where these tools are already in use. More examples and exercises have been added throughout the book. "If I were teaching a course on this subject, I would use this as a resource and text. If I were a student who wanted to learn codesign, I would look for a course that at least used a similar approach. If I were an engineer or engineering manager who wanted to learn more about codesign from a very practical perspective, I would read this book first before any other. When I first started learning about codesign as a practitioner, a book like this would have been the perfect introduction." --Grant Martin, Tensilica--

This book describes a model-based development approach for globally-asynchronous locally-synchronous distributed embedded controllers. This approach uses Petri nets as modeling formalism to create platform and network independent models supporting the use of design automation tools. To support this development approach, the Petri nets class in use is extended with time-domains and asynchronous-channels. The authors' approach uses models not only providing a better understanding of the distributed controller and improving the communication among the stakeholders, but also to be ready to support the entire lifecycle, including the simulation, the verification (using model-checking tools), the implementation (relying on automatic code generators), and the deployment of the distributed controller into specific platforms. Uses a graphical and intuitive modeling formalism supported by design automation tools; Enables verification, ensuring that the distributed controller was correctly specified; Provides flexibility in the implementation and maintenance phases to achieve desired constraints (high performance, low power consumption, reduced costs), enabling porting to different platforms using different communication nodes, without changing the underlying behavioral model.

This book presents three approaches to the analysis of the deadline miss ratio of applications with stochastic task execution times. Each best fits a different context: an exact one efficiently applicable to monoprocessor systems; an approximate one, which allows for designer-controlled trade-off between analysis accuracy and analysis speed; and one less accurate but sufficiently fast in order to be placed inside optimization loops.

This monograph is based on the third author's lectures on computer architecture, given in the summer semester 2013 at Saarland University, Germany. It contains a gate level construction of a multi-core machine with pipelined MIPS processor cores and a sequentially consistent shared memory. The book contains the first correctness proofs for both the gate level implementation of a multi-core processor and also of a cache based sequentially consistent shared memory. This opens the way to the formal verification of synthesizable hardware for multi-core processors in the future. Constructions are in a gate level hardware model and thus deterministic. In contrast the reference models against which correctness is shown are nondeterministic. The development of the additional machinery for these proofs and the correctness proof of the shared memory at the gate level are the main technical contributions of this work.

This book presents techniques for energy reduction in adaptive embedded multimedia systems, based on dynamically reconfigurable processors. The approach described will enable designers to meet performance/area constraints, while minimizing video quality degradation, under various, run-time scenarios. Emphasis is placed on implementing power/energy reduction at various abstraction levels. To enable this, novel techniques for adaptive energy management at both processor architecture and application architecture levels are presented, such that both hardware and software adapt together, minimizing overall energy consumption under unpredictable, design-/compile-time scenarios.

Both authors have taught the course of "Distributed Systems" for many years in the respective schools. During the teaching, we feel strongly that "Distributed systems" have evolved from traditional "LAN" based distributed systems towards "Internet based" systems. Although there exist many excellent textbooks on this topic, because of the fast development of distributed systems and network programming/protocols, we have difficulty in finding an appropriate textbook for the course of "distributed systems" with orientation to the requirement of the undergraduate level study for today's distributed technology. Specifically, from - to-date concepts, algorithms, and models to implementations for both distributed system designs and application programming. Thus the philosophy behind this book is to integrate the concepts, algorithm designs and implementations of distributed systems based on network programming. After using several materials of other textbooks and research books, we found that many texts treat the distributed systems with separation of concepts, algorithm design and network programming and it is very difficult for students to map the concepts of distributed systems to the algorithm design, prototyping and implementations. This book intends to enable readers, especially postgraduates and senior undergraduate level, to study up-to-date concepts, algorithms and network programming skills for building modern distributed systems. It enables students not only to master the concepts of distributed network system but also to readily use the material introduced into implementation practices.

This book describes a specification, microarchitecture, VHDL implementation and evaluation of a SPARC v8 CPU with fine-grain multi-threading, called micro-threading. The CPU, named UTLEON3, is an alternative platform for exploring CPU multi-threading that is compatible with the industry-standard GRLIB package. The processor microarchitecture was designed to map in an efficient way the data-flow scheme on a classical von Neumann pipelined processing used in common processors, while retaining full binary compatibility with existing legacy programs.

It is widely acknowledged that the cost of validation and testing comprises a s- nificant percentage of the overall development costs for electronic systems today, and is expected to escalate sharply in the future. Many studies have shown that up to 70% of the design development time and resources are spent on functional verification. Functional errors manifest themselves very early in the design flow, and unless they are detected up front, they can result in severe consequence- both financially and from a safety viewpoint. Indeed, several recent instances of high-profile functional errors (e. g. , the Pentium FDIV bug) have resulted in - creased attention paid to verifying the functional correctness of designs. Recent efforts have proposed augmenting the traditional RTL simulation-based validation methodology with formal techniques in an attempt to uncover hard-to-find c- ner cases, with the goal of trying to reach RTL functional verification closure. However, what is often not highlighted is the fact that in spite of the tremendous time and effort put into such efforts at the RTL and lower levels of abstraction, the complexity of contemporary embedded systems makes it difficult to guarantee functional correctness at the system level under all possible operational scenarios. The problem is exacerbated in current System-on-Chip (SOC) design meth- ologies that employ Intellectual Property (IP) blocks composed of processor cores, coprocessors, and memory subsystems. Functional verification becomes one of the major bottlenecks in the design of such systems.

This book provides an overview of automatic test pattern generation (ATPG) and introduces novel techniques to complement classical ATPG, based on Boolean Satisfiability (SAT). A fast and highly fault efficient SAT-based ATPG framework is presented which is also able to generate high-quality delay tests such as robust path delay tests, as well as tests with long propagation paths to detect small delay defects. The aim of the techniques and methodologies presented in this book is to improve SAT-based ATPG, in order to make it applicable in industrial practice. Readers will learn to improve the performance and robustness of the overall test generation process, so that the ATPG algorithm reliably will generate test patterns for most targeted faults in acceptable run time to meet the high fault coverage demands of industry. The techniques and improvements presented in this book provide the following advantages: Provides a comprehensive introduction to test generation and Boolean Satisfiability (SAT); Describes a highly fault efficient SAT-based ATPG framework; Introduces circuit-oriented SAT solving techniques, which make use of structural information and are able to accelerate the search process significantly; Provides SAT formulations for the prevalent delay faults models, in addition to the classical stuck-at fault model; Includes an industrial perspective on the state-of-the-art in the testing, along with SAT; two topics typically distinguished from each other.

This book provides the foundations for understanding hardware security and trust, which have become major concerns for national security over the past decade. Coverage includes security and trust issues in all types of electronic devices and systems such as ASICs, COTS, FPGAs, microprocessors/DSPs, and embedded systems. This serves as an invaluable reference to the state-of-the-art research that is of critical significance to the security of, and trust in, modern society's microelectronic-supported infrastructures.

This book introduces a novel design methodology which can significantly reduce the ASIP development effort through high degrees of design automation. The key elements of this new design methodology are a powerful application profiler and an automated instruction-set customization tool which considerably lighten the burden of mapping a target application to an ASIP architecture in the initial design stages. The book includes several design case studies with real life embedded applications to demonstrate how the methodology and the tools can be used in practice for accelerating the overall ASIP design process.