This book offers readers a clear guide to implementing engineering applications with FPGAs, from the mathematical description to the hardware synthesis, including discussion of VHDL programming and co-simulation issues. Coverage includes FPGA realizations such as: chaos generators that are described from their mathematical models; artificial neural networks (ANNs) to predict chaotic time series, for which a discussion of different ANN topologies is included, with different learning techniques and activation functions; random number generators (RNGs) that are realized using different chaos generators, and discussions of their maximum Lyapunov exponent values and entropies. Finally, optimized chaotic oscillators are synchronized and realized to implement a secure communication system that processes black and white and grey-scale images. In each application, readers will find VHDL programming guidelines and computer arithmetic issues, along with co-simulation examples with Active-HDL and Simulink.The whole book provides a practical guide to implementing a variety of engineering applications from VHDL programming and co-simulation issues, to FPGA realizations of chaos generators, ANNs for chaotic time-series prediction, RNGs and chaotic secure communications for image transmission.

This proven textbook guides readers to a thorough understanding of the theory and design of operational amplifiers (OpAmps). The core of the book presents systematically the design of operational amplifiers, classifying them into a periodic system of nine main overall configurations, ranging from one gain stage up to four or more stages. This division enables circuit designers to recognize quickly, understand, and choose optimal configurations. Characterization of operational amplifiers is given by macro models and error matrices, together with measurement techniques for their parameters. Definitions are given for four types of operational amplifiers depending on the grounding of their input and output ports. Many famous designs are evaluated in depth, using a carefully structured approach enhanced by numerous figures. In order to reinforce the concepts introduced and facilitate self-evaluation of design skills, the author includes problems with detailed solutions, as well as simulation exercises.

This book constitutes the refereed proceedings of the 33rd International Conference, ISC High Performance 2018, held in Frankfurt, Germany, in June 2018. The 20 revised full papers presented in this book were carefully reviewed and selected from 81 submissions. The papers cover the following topics: Resource Management and Energy Efficiency; Performance Analysis and Tools; Exascale Networks; Parallel Algorithms.

This book provides a single-source reference on the use of carbon nanotubes (CNTs) as interconnect material for horizontal, on-chip and 3D interconnects. The authors demonstrate the uses of bundles of CNTs, as innovative conducting material to fabricate interconnect through-silicon vias (TSVs), in order to improve the performance, reliability and integration of 3D integrated circuits (ICs). This book will be first to provide a coherent overview of exploiting carbon nanotubes for 3D interconnects covering aspects from processing, modeling, simulation, characterization and applications. Coverage also includes a thorough presentation of the application of CNTs as horizontal on-chip interconnects which can potentially revolutionize the nanoelectronics industry. This book is a must-read for anyone interested in the state-of-the-art on exploiting carbon nanotubes for interconnects for both 2D and 3D integrated circuits.

This book brings together a selection of the best papers from the eighteenth edition of the Forum on specification and Design Languages Conference (FDL), which took place on September 14-16, 2015, in Barcelona, Spain. FDL is a well-established international forum devoted to dissemination of research results, practical experiences and new ideas in the application of specification, design and verification languages to the design, modeling and verification of integrated circuits, complex hardware/software embedded systems, and mixed-technology systems.

This book puts in focus various techniques for checking modeling fidelity of Cyber Physical Systems (CPS), with respect to the physical world they represent. The authors' present modeling and analysis techniques representing different communities, from very different angles, discuss their possible interactions, and discuss the commonalities and differences between their practices. Coverage includes model driven development, resource-driven development, statistical analysis, proofs of simulator implementation, compiler construction, power/temperature modeling of digital devices, high-level performance analysis, and code/device certification. Several industrial contexts are covered, including modeling of computing and communication, proof architectures models and statistical based validation techniques.

This book constitutes the refereed proceedings of the 15th National Conference on Embedded Systems Technology, ESTC 2017, held in Shenyang, China, in November 2017. The 18 revised full papers presented were carefully reviewed and selected from 45 papers. The topics cover a broad range of fields focusing on the theme "embedded systems and intelligent computing," such as context aware computing, scheduling, cyber physical system, high performance embedded computing, embedded system and applications, and education and surveys.

A unique feature of this textbook is to provide a comprehensive introduction to the fundamental knowledge in embedded systems, with applications in cyber-physical systems and the Internet of things. It starts with an introduction to the field and a survey of specification models and languages for embedded and cyber-physical systems. It provides a brief overview of hardware devices used for such systems and presents the essentials of system software for embedded systems, including real-time operating systems. The author also discusses evaluation and validation techniques for embedded systems and provides an overview of techniques for mapping applications to execution platforms, including multi-core platforms. Embedded systems have to operate under tight constraints and, hence, the book also contains a selected set of optimization techniques, including software optimization techniques. The book closes with a brief survey on testing. This third edition has been updated and revised to reflect new trends and technologies, such as the importance of cyber-physical systems and the Internet of things, the evolution of single-core processors to multi-core processors, and the increased importance of energy efficiency and thermal issues.

This textbook for a one-semester course in Digital Systems Design describes the basic methods used to develop "traditional" Digital Systems, based on the use of logic gates and flip flops, as well as more advanced techniques that enable the design of very large circuits, based on Hardware Description Languages and Synthesis tools. It was originally designed to accompany a MOOC (Massive Open Online Course) created at the Autonomous University of Barcelona (UAB), currently available on the Coursera platform. Readers will learn what a digital system is and how it can be developed, preparing them for steps toward other technical disciplines, such as Computer Architecture, Robotics, Bionics, Avionics and others. In particular, students will learn to design digital systems of medium complexity, describe digital systems using high level hardware description languages, and understand the operation of computers at their most basic level. All concepts introduced are reinforced by plentiful illustrations, examples, exercises, and applications. For example, as an applied example of the design techniques presented, the authors demonstrate the synthesis of a simple processor, leaving the student in a position to enter the world of Computer Architecture and Embedded Systems.

This book describes in detail the impact of process variations on Network-on-Chip (NoC) performance. The authors evaluate various NoC topologies under high process variation and explain the design of efficient NoCs, with advanced technologies. The discussion includes variation in logic and interconnect, in order to evaluate the delay and throughput variation with different NoC topologies. The authors describe an asynchronous router, as a robust design to mitigate the impact of process variation in NoCs and the performance of different routing algorithms is determined with/without process variation for various traffic patterns. Additionally, a novel Process variation Delay and Congestion aware Routing algorithm (PDCR) is described for asynchronous NoC design, which outperforms different adaptive routing algorithms in the average delay and saturation throughput for various traffic patterns.

This book constitutes the proceedings of the 39th International Conference on Application and Theory of Petri Nets and Concurrency, PETRI NETS 2018, held in Bratislava, Slovakia, in June 2018. Petri Nets 2017 is co-located with the 19th International Conference on Application of Concurrency to System Design, ACSD 2018. The 15 regular and 8 tool papers, with 1 invited talk presented together in this volume were carefully reviewed and selected from 33 submissions. The focus of the conference is on following topics: Petri Nets Synthesis; Analysis and Model Checking; Languages; Semantics and Expressiveness; and Tools.

This book presents a realistic and a holistic review of the microelectronic and semiconductor technology options in the post Moore's Law regime. Technical tradeoffs, from architecture down to manufacturing processes, associated with the 2.5D and 3D integration technologies, as well as the business and product management considerations encountered when faced by disruptive technology options, are presented. Coverage includes a discussion of Integrated Device Manufacturer (IDM) vs Fabless, vs Foundry, and Outsourced Assembly and Test (OSAT) barriers to implementation of disruptive technology options. This book is a must-read for any IC product team that is considering getting off the Moore's Law track, and leveraging some of the More-than-Moore technology options for their next microelectronic product.

This comprehensive textbook on the field programmable gate array (FPGA) covers its history, fundamental knowledge, architectures, device technologies, computer-aided design technologies, design tools, examples of application, and future trends. Programmable logic devices represented by FPGAs have been rapidly developed in recent years and have become key electronic devices used in most IT products. This book provides both complete introductions suitable for students and beginners, and high-level techniques useful for engineers and researchers in this field. Differently developed from usual integrated circuits, the FPGA has unique structures, design methodologies, and application techniques. Allowing programming by users, the device can dramatically reduce the rising cost of development in advanced semiconductor chips. The FPGA is now driving the most advanced semiconductor processes and is an all-in-one platform combining memory, CPUs, and various peripheral interfaces. This book introduces the FPGA from various aspects for readers of different levels. Novice learners can acquire a fundamental knowledge of the FPGA, including its history, from Chapter 1; the first half of Chapter 2; and Chapter 4. Professionals who are already familiar with the device will gain a deeper understanding of the structures and design methodologies from Chapters 3 and 5. Chapters 6-8 also provide advanced techniques and cutting-edge applications and trends useful for professionals. Although the first parts are mainly suitable for students, the advanced sections of the book will be valuable for professionals in acquiring an in-depth understanding of the FPGA to maximize the performance of the device.

This book provides a comprehensive introduction to hardware security, from specification to implementation. Applications discussed include embedded systems ranging from small RFID tags to satellites orbiting the earth. The authors describe a design and synthesis flow, which will transform a given circuit into a secure design incorporating counter-measures against fault attacks. In order to address the conflict between testability and security, the authors describe innovative design-for-testability (DFT) computer-aided design (CAD) tools that support security challenges, engineered for compliance with existing, commercial tools. Secure protocols are discussed, which protect access to necessary test infrastructures and enable the design of secure access controllers.

This book introduces readers to a variety of tools for automatic analog integrated circuit (IC) sizing and optimization. The authors provide a historical perspective on the early methods proposed to tackle automatic analog circuit sizing, with emphasis on the methodologies to size and optimize the circuit, and on the methodologies to estimate the circuit's performance. The discussion also includes robust circuit design and optimization and the most recent advances in layout-aware analog sizing approaches. The authors describe a methodology for an automatic flow for analog IC design, including details of the inputs and interfaces, multi-objective optimization techniques, and the enhancements made in the base implementation by using machine leaning techniques. The Gradient model is discussed in detail, along with the methods to include layout effects in the circuit sizing. The concepts and algorithms of all the modules are thoroughly described, enabling readers to reproduce the methodologies, improve the quality of their designs, or use them as starting point for a new tool. An extensive set of application examples is included to demonstrate the capabilities and features of the methodologies described.

The three-volume set LNCS 10860, 10861 and 10862 constitutes the proceedings of the 18th International Conference on Computational Science, ICCS 2018, held in Wuxi, China, in June 2018. The total of 155 full and 66 short papers presented in this book set was carefully reviewed and selected from 404 submissions. The papers were organized in topical sections named: Part I: ICCS Main Track Part II: Track of Advances in High-Performance Computational Earth Sciences: Applications and Frameworks; Track of Agent-Based Simulations, Adaptive Algorithms and Solvers; Track of Applications of Matrix Methods in Artificial Intelligence and Machine Learning; Track of Architecture, Languages, Compilation and Hardware Support for Emerging ManYcore Systems; Track of Biomedical and Bioinformatics Challenges for Computer Science; Track of Computational Finance and Business Intelligence; Track of Computational Optimization, Modelling and Simulation; Track of Data, Modeling, and Computation in IoT and Smart Systems; Track of Data-Driven Computational Sciences; Track of Mathematical-Methods-and-Algorithms for Extreme Scale; Track of Multiscale Modelling and Simulation Part III: Track of Simulations of Flow and Transport: Modeling, Algorithms and Computation; Track of Solving Problems with Uncertainties; Track of Teaching Computational Science; Poster Papers

This thesis introduces novel and significant results regarding the analysis and synthesis of positive systems, especially under l1 and L1 performance. It describes stability analysis, controller synthesis, and bounding positivity-preserving observer and filtering design for a variety of both discrete and continuous positive systems. It subsequently derives computationally efficient solutions based on linear programming in terms of matrix inequalities, as well as a number of analytical solutions obtained for special cases. The thesis applies a range of novel approaches and fundamental techniques to the further study of positive systems, thus contributing significantly to the theory of positive systems, a "hot topic" in the field of control.

This book discusses the design and performance analysis of SDRAM controllers that cater to both real-time and best-effort applications, i.e. mixed-time-criticality memory controllers. The authors describe the state of the art, and then focus on an architecture template for reconfigurable memory controllers that addresses effectively the quickly evolving set of SDRAM standards, in terms of worst-case timing and power analysis, as well as implementation. A prototype implementation of the controller in SystemC and synthesizable VHDL for an FPGA development board are used as a proof of concept of the architecture template.

This book introduces new massively parallel computer (MPSoC) architectures called invasive tightly coupled processor arrays. It proposes strategies, architecture designs, and programming interfaces for invasive TCPAs that allow invading and subsequently executing loop programs with strict requirements or guarantees of non-functional execution qualities such as performance, power consumption, and reliability. For the first time, such a configurable processor array architecture consisting of locally interconnected VLIW processing elements can be claimed by programs, either in full or in part, using the principle of invasive computing. Invasive TCPAs provide unprecedented energy efficiency for the parallel execution of nested loop programs by avoiding any global memory access such as GPUs and may even support loops with complex dependencies such as loop-carried dependencies that are not amenable to parallel execution on GPUs. For this purpose, the book proposes different invasion strategies for claiming a desired number of processing elements (PEs) or region within a TCPA exclusively for an application according to performance requirements. It not only presents models for implementing invasion strategies in hardware, but also proposes two distinct design flavors for dedicated hardware components to support invasion control on TCPAs.

This book introduces readers to a variety of tools for analog layout design automation. After discussing the placement and routing problem in electronic design automation (EDA), the authors overview a variety of automatic layout generation tools, as well as the most recent advances in analog layout-aware circuit sizing. The discussion includes different methods for automatic placement (a template-based Placer and an optimization-based Placer), a fully-automatic Router and an empirical-based Parasitic Extractor. The concepts and algorithms of all the modules are thoroughly described, enabling readers to reproduce the methodologies, improve the quality of their designs, or use them as starting point for a new tool. All the methods described are applied to practical examples for a 130nm design process, as well as placement and routing benchmark sets.

This book provides the most comprehensive and consistent survey of the field of IC design for Biological Sensing and Processing. The authors describe a multitude of applications that require custom CMOS IC design and highlight the techniques in analog and mixed-signal circuit design that potentially can cross boundaries and benefit the very wide community of bio-medical engineers.

This book presents a new optimization flow for quantum circuits realization. At the reversible level, optimization algorithms are presented to reduce the quantum cost. Then, new mapping approaches to decompose reversible circuits to quantum circuits using different quantum libraries are described. Finally, optimization techniques to reduce the quantum cost or the delay are applied to the resulting quantum circuits. Furthermore, this book studies the complexity of reversible circuits and quantum circuits from a theoretical perspective.

This book describes state-of-the-art techniques for designing real-time computer systems. The author shows how to estimate precisely the effect of cache architecture on the execution time of a program, how to dispatch workload on multicore processors to optimize resources, while meeting deadline constraints, and how to use closed-form mathematical approaches to characterize highly variable workloads and their interaction in a networked environment. Readers will learn how to deal with unpredictable timing behaviors of computer systems on different levels of system granularity and abstraction.

This book constitutes the refereed proceedings of the 9th International Workshop on Post-Quantum Cryptography, PQCrypto 2018, held in Fort Lauderdale, FL, USA, in April 2018. The 24 revised full papers presented were carefully reviewed and selected from 97 submissions. The papers are organized in topical sections on Code-based Cryptography; Cryptanalysis; Hash-based Cryptography; Isogenies in Cryptography; Lattice-based Cryptography; Multivariate Cryptography; Protocols; Quantum Algorithms.

This book provides a comprehensive overview of flow-based, microfluidic VLSI. The authors describe and solve in a comprehensive and holistic manner practical challenges such as control synthesis, wash optimization, design for testability, and diagnosis of modern flow-based microfluidic biochips. They introduce practical solutions, based on rigorous optimization and formal models. The technical contributions presented in this book will not only shorten the product development cycle, but also accelerate the adoption and further development of modern flow-based microfluidic biochips, by facilitating the full exploitation of design complexities that are possible with current fabrication techniques.