The modern electronic testing has a forty year history. Test professionals hold some fairly large conferences and numerous workshops, have a journal, and there are over one hundred books on testing. Still, a full course on testing is offered only at a few universities, mostly by professors who have a research interest in this area. Apparently, most professors would not have taken a course on electronic testing when they were students. Other than the computer engineering curriculum being too crowded, the major reason cited for the absence of a course on electronic testing is the lack of a suitable textbook. For VLSI the foundation was provided by semiconductor device techn- ogy, circuit design, and electronic testing. In a computer engineering curriculum, therefore, it is necessary that foundations should be taught before applications. The field of VLSI has expanded to systems-on-a-chip, which include digital, memory, and mixed-signalsubsystems. To our knowledge this is the first textbook to cover all three types of electronic circuits. We have written this textbook for an undergraduate "foundations" course on electronic testing. Obviously, it is too voluminous for a one-semester course and a teacher will have to select from the topics. We did not restrict such freedom because the selection may depend upon the individual expertise and interests. Besides, there is merit in having a larger book that will retain its usefulness for the owner even after the completion of the course. With equal tenacity, we address the needs of three other groups of readers.

In the past decade, substrate noise has had a constant and significant impact on the design of analog and mixed-signal integrated circuits. Only recently, with advances in chip miniaturization and innovative circuit design, has substrate noise begun to plague fully digital circuits as well. To combat the effects of substrate noise, heavily over-designed structures are generally adopted, thus seriously limiting the advantages of innovative technologies. Substrate Noise: Analysis and Optimization for IC Design addresses the main problems posed by substrate noise from both an IC and a CAD designer perspective. The effects of substrate noise on performance in digital, analog, and mixed-signal circuits are presented, along with the mechanisms underlying noise generation, injection, and transport. Popular solutions to the substrate noise problem and the trade-offs often debated by designers are extensively discussed. Non-traditional approaches as well as semi-automated techniques to combat substrate noise are also addressed. Substrate Noise: Analysis and Optimization for IC Design will be of interest to researchers and professionals interested in signal integrity, as well as to mixed signal and RF designers.

Over the last 15 years, the application of innovative steel concepts in the automotive industry has increased steadily. Numerical simulation technology of hot forming of high-strength steel allows engineers to modify the formability of hot forming steel metals and to optimize die design schemes. Theories, Methods and Numerical Technology of Sheet Metal Cold and Hot Forming focuses on hot and cold forming theories, numerical methods, relative simulation and experiment techniques for high-strength steel forming and die design in the automobile industry. Theories, Methods and Numerical Technology of Sheet Metal Cold and Hot Forming introduces the general theories of cold forming, then expands upon advanced hot forming theories and simulation methods, including: the forming process, constitutive equations, hot boundary constraint treatment, and hot forming equipment and experiments. Various calculation methods of cold and hot forming, based on the authors' experience in commercial CAE software for sheet metal forming, are provided, as well as a discussion of key issues, such as hot formability with quenching process, die design and cooling channel design in die, and formability experiments. Theories, Methods and Numerical Technology of Sheet Metal Cold and Hot Forming will enable readers to develop an advanced knowledge of hot forming, as well as to apply hot forming theories, calculation methods and key techniques to direct their die design. It is therefore a useful reference for students and researchers, as well as automotive engineers.

Computing increasingly happens somewhere, with that geographic location important to the computational process itself. Many new and evolving spatial technologies, such as geosensor networks and smartphones, embody this trend. Conventional approaches to spatial computing are centralized, and do not account for the inherently decentralized nature of "computing somewhere": the limited, local knowledge of individual system components, and the interaction between those components at different locations. On the other hand, despite being an established topic in distributed systems, decentralized computing is not concerned with geographical constraints to the generation and movement of information. In this context, of (centralized) spatial computing and decentralized (non-spatial) computing, the key question becomes: "What makes decentralized spatial computing special?" In Part I of the book the author covers the foundational concepts, structures, and design techniques for decentralized computing with spatial and spatiotemporal information. In Part II he applies those concepts and techniques to the development of algorithms for decentralized spatial computing, stepping through a suite of increasingly sophisticated algorithms: from algorithms with minimal spatial information about their neighborhoods; to algorithms with access to more detailed spatial information, such as direction, distance, or coordinate location; to truly spatiotemporal algorithms that monitor environments that are dynamic, even using networks that are mobile or volatile. Finally, in Part III the author shows how decentralized spatial and spatiotemporal algorithms designed using the techniques explored in Part II can be simulated and tested. In particular, he investigates empirically the important properties of a decentralized spatial algorithm: its computational efficiency and its robustness to unavoidable uncertainty. Part III concludes with a survey of the opportunities for connecting decentralized spatial computing to ongoing research and emerging hot topics in related fields, such as biologically inspired computing, geovisualization, and stream computing. The book is written for students and researchers of computer science and geographic information science. Throughout the book the author's style is characterized by a focus on the broader message, explaining the process of decentralized spatial algorithm design rather than the technical details. Each chapter ends with review questions designed to test the reader's understanding of the material and to point to further work or research. The book includes short appendices on discrete mathematics and SQL. Simulation models written in NetLogo and associated source code for all the algorithms presented in the book can be found on the author's accompanying website.

I am glad to see this new book on the e language and on verification. I am especially glad to see a description of the e Reuse Methodology (eRM). The main goal of verification is, after all, finding more bugs quicker using given resources, and verification reuse (module-to-system, old-system-to-new-system etc. ) is a key enabling component. This book offers a fresh approach in teaching the e hardware verification language within the context of coverage driven verification methodology. I hope it will help the reader und- stand the many important and interesting topics surrounding hardware verification. Yoav Hollander Founder and CTO, Verisity Inc. Preface This book provides a detailed coverage of the e hardware verification language (HVL), state of the art verification methodologies, and the use of e HVL as a facilitating verification tool in implementing a state of the art verification environment. It includes comprehensive descriptions of the new concepts introduced by the e language, e language syntax, and its as- ciated semantics. This book also describes the architectural views and requirements of verifi- tion environments (randomly generated environments, coverage driven verification environments, etc. ), verification blocks in the architectural views (i. e. generators, initiators, c- lectors, checkers, monitors, coverage definitions, etc. ) and their implementations using the e HVL. Moreover, the e Reuse Methodology (eRM), the motivation for defining such a gui- line, and step-by-step instructions for building an eRM compliant e Verification Component (eVC) are also discussed.

Regular Fabrics in Deep Sub-Micron Integrated-Circuit Design discusses new approaches to better timing-closure and manufacturability of DSM Integrated Circuits. The key idea presented is the use of regular circuit and interconnect structures such that area/delay can be predicted with high accuracy. The co-design of structures and algorithms allows great opportunities for achieving better final results, thus closing the gap between IC and CAD designers. The regularities also provide simpler and possibly better manufacturability. In this book we present not only algorithms for solving particular sub-problems but also systematic ways of organizing different algorithms in a flow to solve the design problem as a whole. A timing-driven chip design flow is developed based on the new structures and their design algorithms, which produces faster chips in a shorter time.

As integrated circuit (IC) feature sizes scaled below a quarter of a micron, thereby defining the deep submicron (DSM) era, there began a gradual shift in the impact on performance due to the metal interconnections among the active circuit components. Once viewed as merely parasitics in terms of their relevance to the overall circuit behavior, the interconnect can now have a dominant impact on the IC area and performance. Beginning in the late 1980's there was significant research toward better modeling and characterization of the resistance, capacitance and ultimately the inductance of on-chip interconnect. IC Interconnect Analysis covers the state-of-the-art methods for modeling and analyzing IC interconnect based on the past fifteen years of research. This is done at a level suitable for most practitioners who work in the semiconductor and electronic design automation fields, but also includes significant depth for the research professionals who will ultimately extend this work into other areas and applications. IC Interconnect Analysis begins with an in-depth coverage of delay metrics, including the ubiquitous Elmore delay and its many variations. This is followed by an outline of moment matching methods, calculating moments efficiently, and Krylov subspace methods for model order reduction. The final two chapters describe how to interface these reduced-order models to circuit simulators and gate-level timing analyzers respectively. IC Interconnect Analysis is written for CAD tool developers, IC designers and graduate students.

The proliferation and growth of Electronic Design Automation (EDA) has spawned many diverse and interesting technologies. One of the most prominent of these technologies is the VHSIC Hardware Description Language, or VHDL. VHDL permits designers of digital modules, components, systems, and even networks to describe their designs both structurally and behaviorally. VHDL also allows simulation of the designs in order to investigate their performance prior to actually implementing them in hardware. Having gained the ability to simulate designs once encoded in VHDL, designers were naturally confronted with the issue of testing these designs. VHDL did not explicitly address the requirement to insert particular digital waveforms, often termed test vectors or patterns, or to subsequently assess the correctness of the response from some digital entity. In a distributed design environment, or even in an isolated one where the design was subject to review or scrutiny by another organization, de-facto methods of testing and evaluating results proved faulty. The reason was a lack of standardization.When organization A designed a circuit and tested it with their self-developed test tools it had a certain behavior. When it was delivered to organization B and B tested it using their test tools, the behavior was different. Was the fault in the circuit, in A's tools, or in B's tools? The only way to resolve this was for both organizations to agree on a test apparatus, validate its correctness and use it consistently. While VHDL was an IEEE standard language, and consistency among myriad designers was fairly well guaranteed, no such standard existed for test waveform generation and assessment. Hence, the value of standardization in the design language was being negated by the lack of such a standard for testing. The Waveform and Vector Exchange Specification, or WAVES, was conceived and designed to solve this testing problem -- and it has. Being both a subset of VHDL itself, as well as an IEEE standard, it guarantees both conformity among multiple applications and easy integration with VHDL units under test (UUTs). Using WAVES and VHDL for Effective Design and Testing will serve many purposes.For the WAVES beginner, its tutorial will make the application of WAVES in typical, standard usage straightforward and convenient. For the more advanced user, the advanced topics will provide insight into the nuances of these useful capabilities. For all users, the tools, templates and examples given in the chapters, as well as on the companion disk, will provide a practical starting foundation for using WAVES and VHDL.

Engineering productivity in integrated circuit product design and - velopment today is limited largely by the effectiveness of the CAD tools used. For those domains of product design that are highly dependent on transistor-level circuit design and optimization, such as high-speed logic and memory, mixed-signal analog-digital int- faces, RF functions, power integrated circuits, and so forth, circuit simulation is perhaps the single most important tool. As the complexity and performance of integrated electronic systems has increased with scaling of technology feature size, the capabilities and sophistication of the underlying circuit simulation tools have correspondingly increased. The absolute size of circuits requiring transistor-level simulation has increased dramatically, creating not only problems of computing power resources but also problems of task organization, complexity management, output representation, initial condition setup, and so forth. Also, as circuits of more c- plexity and mixed types of functionality are attacked with simu- tion, the spread between time constants or event time scales within the circuit has tended to become wider, requiring new strategies in simulators to deal with large time constant spreads.

VHDL Coding Styles and Methodologies was originally written as a teaching tool for a VHDL training course. The author began writing the book because he could not find a practical and easy to read book that gave in depth coverage of both, the language and coding methodologies. This book is intended for: 1. College students. It is organized in 13 chapters, each covering a separate aspect of the language, with complete examples. All VHDL code described in the book is on a companion 3.5" PC disk. Students can compile and simulate the examples to get a greater understanding of the language. Each chapter includes a series of exercises to reinforce the concepts. 2. Engineers. It is written by an aerospace engineer who has 26 years of hardware, software, computer architecture and simulation experience. It covers practical applications ofVHDL with coding styles and methodologies that represent what is current in the industry. VHDL synthesizable constructs are identified. Guidelines for testbench designs are provided. Also included is a project for the design of a synthesizable Universal Asynchronous Receiver Transmitter (UART), and a testbench to verify proper operation of the UART in a realistic environment, with CPU interfaces and transmission line jitter. An introduction to VHDL Initiative Toward ASIC Libraries (VITAL) is also provided. The book emphasizes VHDL 1987 standard but provides guidelines for features implemented in VHDL 1993.

by Kurt Keutzer Those looking for a quick overview of the book should fast-forward to the Introduction in Chapter 1. What follows is a personal account of the creation of this book. The challenge from Earl Killian, formerly an architect of the MIPS processors and at that time Chief Architect at Tensilica, was to explain the significant performance gap between ASICs and custom circuits designed in the same process generation. The relevance of the challenge was amplified shortly thereafter by Andy Bechtolsheim, founder of Sun Microsystems and ubiquitous investor in the EDA industry. At a dinner talk at the 1999 International Symposium on Physical Design, Andy stated that the greatest near-term opportunity in CAD was to develop tools to bring the performance of ASIC circuits closer to that of custom designs. There seemed to be some synchronicity that two individuals so different in concern and character would be pre-occupied with the same problem. Intrigued by Earl and Andy's comments, the game was afoot. Earl Killian and other veterans of microprocessor design were helpful with clues as to the sources of the performance discrepancy: layout, circuit design, clocking methodology, and dynamic logic. I soon realized that I needed help in tracking down clues. Only at a wonderful institution like the University of California at Berkeley could I so easily commandeer an ab- bodied graduate student like David Chinnery with a knowledge of architecture, circuits, computer-aided design and algorithms.

The Analog to Digital Converters represent one half of the link between the world we live in - analog - and the digital world of computers, which can handle the computations required in digital signal processing. These devices are mathematically very complex due to their nonlinear behavior and thus fairly difficult to analyze without the use of simulation tools. High Speed A/D Converters: Understanding Data Converters Through SPICE presents the subject from the practising engineer's point of view rather than from the academic's point of view. A practical approach is emphasized. High Speed A/D Converters: Understanding Data Converters Through SPICE is intended as a learning tool by providing building blocks that can be stacked on top of each other to build higher order systems. The book provides a guide to understanding the various topologies used in A/D converters by suggesting simple methods for the blocks used in an A/D converter. The converters discussed throughout the book constitute a class of devices called undersampled or Nyquist converters.The tools used in deriving the results presented are: * TopSpice(R) by Penzar - a mixed mode SPICE simulator - version 5.90. The files included in Appendix A were written for this tool. However, most circuit files need only minor adjustments to be used on other SPICE simulators such as PSpice, Hspice, IS_Spice and Micro-Cap IV; * Mathcad 2000 - Professional by Mathsoft. This tool is very useful in performing FFT analysis as well as drawing some of the graphs. Again, the mathcad files are included to help the user analyze the data. High Speed A/D Converters: Understanding Data Converters Through SPICE not only supplies the models for the A/D converters for SPICE program but also describes the physical reasons for the converter's performance.

Verilog(R) Quickstart is a basic, practical, introductory textbook for professionals and students alike. This book explains how a designer can be more effective through the use of the Verilog hardware description language to simulate and document a design. By understanding simulation, a designer can simulate a design to see if a design works before it is built. This gives the designer an opportunity to try different ideas. Documentation allows a designer to maintain and reuse a design more easily. Verilog's intrinsic hierarchical modularity enables the designer to easily reuse portions of the design as 'intellectual property' or 'macro-cells'. Verilog(R) Quickstart presents some of the formal Verilog syntax and definitions and then shows practical uses. This book does not oversimplify the Verilog language nor does it emphasize theory. Verilog(R) Quickstart has over 100 examples that are used to illustrate aspects of the language. In the later chapters the focus is on working with modeling style and explaining why and when one would use different elements of the language. Another feature of the book is the chapter on state machine modeling.There is also a chapter on test benches and testing strategy as well as a chapter on debugging. Verilog(R) Quickstart is designed to teach the Verilog language, to show the designer how to model in Verilog and to explain the basics of using Verilog simulators.

The current trend towards the realization of complex and versatile Systems on a Chip requires the combined efforts and attention of experts in a wide range of areas including microsystems, embedded hardware/software systems, dedicated ASIC and programmable logic hardware, reconfigurable computing, wireless communications and RF issues, video and image processing, memory systems, low power design techniques, design, test and verification algorithms, modeling and simulation, logic synthesis, and interconnect analysis. Thus, the contributions presented herein address a wide range of Systems on a Chip problems. VLSI: Systems on a Chip comprises the selected proceedings of the Tenth International Conference on Very Large Scale Integration (VLSI '99), which was sponsored by the International Federation for Information Processing (IFIP) and was held in Lisbon, Portugal, in December 1999.The volume is organized around two themes, in which the following topics are addressed: VLSI Systems Design and Applications * Analog Systems Design * Analog Modeling and Design * Image Processing * Reconfigurable Computing * Memory and System Design * Low Power Design VLSI Design Methods and CAD * Test and Verification * Analog CAD and Interconnect * Fundamental CAD Algorithms * Verification and Simulation * CAD for Physical Design * High-Level Synthesis and Verification of Embedded Systems VLSI: Systems on a Chip is essential reading for researchers working on system integration, design, and CAD.

Nonlinear physics continues to be an area of dynamic modern research, with applications to physics, engineering, chemistry, mathematics, computer science, biology, medicine and economics. In this text extensive use is made of the Mathematica computer algebra system. No prior knowledge of Mathematica or programming is assumed. This book includes 33 experimental activities that are designed to deepen and broaden the reader's understanding of nonlinear physics. These activities are correlated with Part I, the theoretical framework of the text.

Principles of Verifiable RTL Design: A Functional Coding Style Supporting Verification Processes in Verilog explains how you can write Verilog to describe chip designs at the RT-level in a manner that cooperates with verification processes. This cooperation can return an order of magnitude improvement in performance and capacity from tools such as simulation and equivalence checkers. It reduces the labor costs of coverage and formal model checking by facilitating communication between the design engineer and the verification engineer. It also orients the RTL style to provide more useful results from the overall verification process. The intended audience for Principles of Verifiable RTL Design: A Functional Coding Style Supporting Verification Processes in Verilog is engineers and students who need an introduction to various design verification processes and a supporting functional Verilog RTL coding style. A second intended audience is engineers who have been through introductory training in Verilog and now want to develop good RTL writing practices for verification. A third audience is Verilog language instructors who are using a general text on Verilog as the course textbook but want to enrich their lectures with an emphasis on verification. A fourth audience is engineers with substantial Verilog experience who want to improve their Verilog practice to work better with RTL Verilog verification tools. A fifth audience is design consultants searching for proven verification-centric methodologies. A sixth audience is EDA verification tool implementers who want some suggestions about a minimal Verilog verification subset. Principles of Verifiable RTL Design: A Functional Coding Style Supporting Verification Processes in Verilog is based on the reality that comes from actual large-scale product design process and tool experience.

The manufacturing industry will reap significant benefits from encouraging the development of digital manufacturing science and technology. Digital Manufacturing Science uses theorems, illustrations and tables to introduce the definition, theory architecture, main content, and key technologies of digital manufacturing science. Readers will be able to develop an in-depth understanding of the emergence and the development, the theoretical background, and the techniques and methods of digital manufacturing science. Furthermore, they will also be able to use the basic theories and key technologies described in Digital Manufacturing Science to solve practical engineering problems in modern manufacturing processes. Digital Manufacturing Science is aimed at advanced undergraduate and postgraduate students, academic researchers and researchers in the manufacturing industry. It allows readers to integrate the theories and technologies described with their own research works, and to propose new ideas and new methods to improve the theory and application of digital manufacturing science.

Field-programmable logic has been available for a number of years. The role of Field-Programmable Logic Devices (FPLDs) has evolved from simply implementing the system 'glue-logic' to the ability to implement very complex system functions, such as microprocessors and microcomputers. The speed with which these devices can be programmed makes them ideal for prototyping. Low production cost makes them competitive for small to medium volume productions. These devices make possible new sophisticated applications, and bring up new hardware/software trade-offs and diminish the traditional hardware/software demarcation line. Advanced design tools are being developed for automatic compilation of complex designs and routings to custom circuits. Digital Systems Design and Prototyping Using Field Programmable Logic covers the subjects of digital systems design and (FPLDs), combining them into an entity useful for designers in the areas of digital systems and rapid system prototyping. It is also useful for the growing community of engineers and researchers dealing with the exciting field of FPLDs, reconfigurable and programmable logic.The authors' goal is to bring these topics to students studying digital system design, computer design, and related subjects in order to show them how very complex circuits can be implemented at the desk. Digital Systems Design and Prototyping Using Field Programmable Logic makes a pioneering effort to present rapid prototyping and generation of computer systems using FPLDs. From the Foreword: 'This is a ground-breaking book that bridges the gap between digital design theory and practice. It provides a unifying terminology for describing FPLD technology. In addition to introducing the technology it also describes the design methodology and tools required to harness this technology. It introduces two hardware description languages (e.g. AHDL and VHDL). Design is best learned by practice and the book supports this notion with abundant case studies.' Daniel P. Siewiorek, Carnegie Mellon University CD-ROM INCLUDED Digital Systems Design and Prototyping Using Field Programmable Logic, First Edition includes a CD-ROM that contains Altera's MAX+PLUS II 7.21 Student Edition Programmable Logic Development Software.MAX+PLUS II is a fully integrated design environment that offers unmatched flexibility and performance. The intuitive graphical interface is complemented by complete and instantly accessible on-line documentation, which makes learning and using MAX+PLUS II quick and easy. The MAX+PLUS II version 7.21 Student Edition offers the following features: * Operates on PCs running Windows 3.1, Windows 95 and Windows NT 3.51 and 4.0. * Graphical and text-based design entry, including the Altera Hardware Description Language (AHDL) and VHDL. * Design compilation for Product-term (MAX 7000S) and look-up table (FLEX 10K) device architectures. * Design verification with full timing simulation.

IFIP Working Group 5.2 has organized a series of workshops extending the concept of intelligent CAD to the concept of knowledge intensive engineering. The concept advocates that intensive life-cycle knowledge regarding products and design processes must be incorporated in the center of the CAD architecture. It focuses on the systematization and sharing of knowledge across the life-cycle stages and organizational boundaries. From Knowledge Intensive CAD to Knowledge Intensive Engineering comprises the Proceedings of the Fourth Workshop on Knowledge Intensive CAD, which was sponsored by the International Federation for Information Processing (IFIP) and held in Parma, Italy in May 2000. This workshop looked at the evolution of knowledge intensive design for the product life cycle moving towards knowledge intensive engineering. The 18 selected papers present an overview of the state-of-the-art in knowledge intensive engineering, discussing theoretical aspects and also practical systems and experiences gained in this area.An invited speaker paper is also included, discussing the role of knowledge in product and process innovation and technology for processing semantic knowledge. Main issues discussed in the book are: * Architectures for knowledge intensive CAD; * Tools for knowledge intensive CAD; * Methodologies for knowledge intensive CAD; * Implementation of knowledge intensive CAD; * Applications of knowledge intensive CAD; * Evolution of knowledge intensive design for the life-cycle; * Formal methods. The volume is essential reading for researchers, graduate and postgraduate students, systems developers of advanced computer-aided design and manufacturing systems, and engineers involved in industrial applications.

This volume is a welcome effort towards improving some of the practices in chip design today. The authors provide a comprehensive reference work on Automatic Layout Modification which will be valuable to VLSI courses at universities, and to CAD and circuit engineers and engineering managers.

These proceedings contain lectures presented at the NATO-NSF-ARO sponsored Advanced Study I stitute on "Computer Aided Analysis and Optimization of Mechanical System Dynamics" held in Iowa City, Iowa, 1-12 August, 1983. Lectures were presented by free world leaders in the field of machine dynamics and optimization. Participants in the Institute were specialists from throughout NATO, many of whom presented contributed papers during the Institute and all of whom participated actively in discussions on technical aspects of the subject. The proceedings are organized into five parts, each addressing a technical aspect of the field of computational methods in dynamic analysis and design of mechanical systems. The introductory paper presented first in the text outlines some of the numerous technical considerations that must be given to organizing effective and efficient computational methods and computer codes to serve engineers in dynamic analysis and design of mechanical systems. Two substantially different approaches to the field are identified in this introduction and are given attention throughout the text. The first and most classical approach uses a minimal set of Lagrangian generalized coordinates to formulate equations of motion with a small number of constraints. The second method uses a maximal set of cartesian coordinates and leads to a large number of differential and algebraic constraint equations of rather simple form. These fundamentally different approaches and associated methods of symbolic computation, numerical integration, and use of computer graphics are addressed throughout the proceedings.

Embedded systems are informally defined as a collection of programmable parts surrounded by ASICs and other standard components, that interact continuously with an environment through sensors and actuators. The programmable parts include micro-controllers and Digital Signal Processors (DSPs). Embedded systems are often used in life-critical situations, where reliability and safety are more important criteria than performance. Today, embedded systems are designed with an ad hoc approach that is heavily based on earlier experience with similar products and on manual design. Use of higher-level languages such as C helps structure the design somewhat, but with increasing complexity it is not sufficient. Formal verification and automatic synthesis of implementations are the surest ways to guarantee safety. Thus, the POLIS system which is a co-design environment for embedded systems is based on a formal model of computation. POLIS was initiated in 1988 as a research project at the University of California at Berkeley and, over the years, grew into a full design methodology with a software system supporting it. Hardware-Software Co-Design of Embedded Systems: The POLIS Approach is intended to give a complete overview of the POLIS system including its formal and algorithmic aspects. Hardware-Software Co-Design of Embedded Systems: The POLIS Approach will be of interest to embedded system designers (automotive electronics, consumer electronics and telecommunications), micro-controller designers, CAD developers and students.

The modern wireless communication industry has put great demands on circuit designers for smaller, cheaper transceivers in the gigahertz frequency range. One tool which has assisted designers in satisfying these requirements is the use of on-chip inductiveelements (inductors and transformers) in silicon (Si) radio-frequency (RF) integrated circuits (ICs). These elements allow greatly improved levels of performance in Si monolithic low-noise amplifiers, power amplifiers, up-conversion and down-conversion mixers and local oscillators. Inductors can be used to improve the intermodulation distortion performance and noise figure of small-signal amplifiers and mixers. In addition, the gain of amplifier stages can be enhanced and the realization of low-cost on-chip local oscillators with good phase noise characteristics is made feasible. In order to reap these benefits, it is essential that the IC designer be able to predict and optimize the characteristics of on-chip inductiveelements. Accurate knowledge of inductance values, quality factor (Q) and the influence of ad- cent elements (on-chip proximity effects) and substrate losses is essential. In this book the analysis, modeling and application of on-chip inductive elements is considered. Using analyses based on Maxwells equations, an accurate and efficient technique is developed to model these elements over a wide frequency range. Energy loss to the conductive substrate is modeled through several mechanisms, including electrically induced displacement and conductive c- rents and by magnetically induced eddy currents. These techniques have been compiled in a user-friendly software tool ASITIC (Analysis and Simulation of Inductors and Transformers for Integrated Circuits).

Physicians, lawyers, engineers, architects, financial analysts, and other pro fessionals articulate an increasing need for support by intelligent workstations for decision making, analysis, communication, and other activities. "Intelligent Workstations for Professionals" is the collection of papers presented by inter national scientists at a symposium and workshop in March 1992. Requirements from potential users, studies of their behavior as well as approaches and aspects oftechnical realizations of "intelligent" functions are introduced. Eight contributions from members of the Center for Information and Tele communication Technology (Clrn of Northwestern University, Wisconsin Whitewater University, and the Children's Memorial Hospital deal with the latest findings of the UNIS (Users' Needs for Intelligent Systems) project, which is designed to identify needs and wishes from professionals for intelligent sup port systems and the potential barriers to adoption and use of such systems. The remaining papers concentrate on new approaches and techniques that en hance the "intelligence" of future workstations. They tackle issues like architectural trends in workstation design, the combination of workstations with HDTV and speech processing, automatic reading and understanding of documents, the automated development of software, or the processing of in exact knowledge. These papers were contributed by members of the DFKI GmbH (German Research Institute for Artificial Intelligence), GMD mbH (German Society for Mathematics and Data Processing), Siemens Gammasonics Inc., Siemens Nixdorf Informationssysteme AG and Siemens AG."

Design and Analysis of Distributed Embedded Systems is organized similar to the conference. Chapters 1 and 2 deal with specification methods and their analysis while Chapter 6 concentrates on timing and performance analysis. Chapter 3 describes approaches to system verification at different levels of abstraction. Chapter 4 deals with fault tolerance and detection. Middleware and software reuse aspects are treated in Chapter 5. Chapters 7 and 8 concentrate on the distribution related topics such as partitioning, scheduling and communication. The book closes with a chapter on design methods and frameworks.