The assembly sector is one of the least automated in the manufacturing industry. Automation is essential if industrial companies are to be competitive in the future. In assembly, an integrated and flexible approach is needed because 75% of the applications are produced in small and medium batches. The methodologies developed in this book deal with the integration of the assembly process from the initial design of the product to its production. In such an integrated system, assembly planning is one of the most important features. A well-chosen assembly plan will reduce both the number of tool changes and the fixtures within the assembly cell. It will prevent the handling of unstable subassemblies, simplify the design of the robot grippers and reduce production costs. An automatic generator of assembly sequences can be an efficient aid to the designer. Whenever he or she modifies features of the product, the influence of these modifications can immediately be checked on the sequences. For small batch production, the automatic generation of assembly sequences is faster, more reliable and more cost-effective than manual generation. By using this latter method interesting sequences could be missed because of the combinatorial explosion of solutions. The main subjects treated in this book are as follows. 1. Presentation and classification of existing systems of automatic generation of assembly sequences. Automatic assembly planning is, indeed, a very recent research area and, in my experience, no systematic study has been carried out up to now.

This book is a collection of several tutorials from the EUROGRAPHICS '90 conference in Montreux. The conference was held under the motto "IMAGES: Synthesis, Analysis and Interaction", and the tutorials, partly presented in this volume, reflect the conference theme. As such, this volume provides a unique collection of advanced texts on 'traditional' com puter graphics as well as of tutorials on image processing and image reconstruction. As with all the volumes of the series "Advances in Computer Graphics", the contributors are leading experts in their respective fields. The chapter Design and Display of Solid Models provides an extended introduction to interactive graphics techniques for design, fast display, and high-quality rendering of solid models. The text focuses on techniques for Constructive Solid Geometry (CSG). The follow ing topics are treated in depth: interactive design techniques (specification of curves, surfaces and solids; graphical user interfaces; procedural languages and direct manipulation) and display techniques (depth-buffer, scan-line and ray-tracing techniques; CSG classification techniques; efficiency-improving methods; software and hardware implementations).

Since the early 1980s, CAD frameworks have received a great deal of attention, both in the research community and in the commercial arena. It is generally agreed that CAD framework technology promises much: advanced CAD frameworks can turn collections of individual tools into effective and user-friendly design environments. But how can this promise be fulfilled? CAD Frameworks: Principles and Architecture describes the design and construction of CAD frameworks. It presents principles for building integrated design environments and shows how a CAD framework can be based on these principles. It derives the architecture of a CAD framework in a systematic way, using well-defined primitives for representation. This architecture defines how the many different framework sub-topics, ranging from concurrency control to design flow management, relate to each other and come together into an overall system. The origin of this work is the research and development performed in the context of the Nelsis CAD Framework, which has been a working system for well over eight years, gaining functionality while evolving from one release to the next. The principles and concepts presented in this book have been field-tested in the Nelsis CAD Framework. CAD Frameworks: Principles and Architecture is primarily intended for EDA professionals, both in industry and in academia, but is also valuable outside the domain of electronic design. Many of the principles and concepts presented are also applicable to other design-oriented application domains, such as mechanical design or computer-aided software engineering (CASE). It is thus a valuable reference for all those involved in computer-aided design.

In 1998-99, at the dawn of the SoC Revolution, we wrote Surviving the SOC Revolution: A Guide to Platform Based Design. In that book, we focused on presenting guidelines and best practices to aid engineers beginning to design complex System-on-Chip devices (SoCs). Now, in 2003, facing the mid-point of that revolution, we believe that it is time to focus on winning.

In this book, Winning the SoC Revolution: Experiences in Real Design, we gather the best practical experiences in how to design SoCs from the most advanced design groups, while setting the issues and techniques in the context of SoC design methodologies. As an edited volume, this book has contributions from the leading design houses who are winning in SoCs - Altera, ARM, IBM, Philips, TI, UC Berkeley, and Xilinx. These chapters present the many facets of SoC design - the platform based approach, how to best utilize IP, Verification, FPGA fabrics as an alternative to ASICs, and next generation process technology issues. We also include observations from Ron Wilson of CMP Media on best practices for SoC design team collaboration. We hope that by utilizing this book, you too, will win the SoC Revolution.

This is a milestone in machine-assisted microprocessor verification. Gordon [20] and Hunt [32] led the way with their verifications of sim ple designs, Cohn [12, 13] followed this with the verification of parts of the VIPER microprocessor. This work illustrates how much these, and other, pioneers achieved in developing tractable models, scalable tools, and a robust methodology. A condensed review of previous re search, emphasising the behavioural model underlying this style of verification is followed by a careful, and remarkably readable, ac count of the SECD architecture, its formalisation, and a report on the organisation and execution of the automated correctness proof in HOL. This monograph reports on Graham's MSc project, demonstrat ing that - in the right hands - the tools and methodology for formal verification can (and therefore should?) now be applied by someone with little previous expertise in formal methods, to verify a non-trivial microprocessor in a limited timescale. This is not to belittle Graham's achievement; the production of this proof, work ing as Graham did from the previous literature, goes well beyond a typical MSc project. The achievement is that, with this exposition to hand, an engineer tackling the verification of similar microprocessor designs will have a clear view of the milestones that must be passed on the way, and of the methods to be applied to achieve them.

Evolutionary Algorithms for Embedded System Design describes how Evolutionary Algorithm (EA) concepts can be applied to circuit and system design - an area where time-to-market demands are critical. EAs create an interesting alternative to other approaches since they can be scaled with the problem size and can be easily run on parallel computer systems. This book presents several successful EA techniques and shows how they can be applied at different levels of the design process. Starting on a high-level abstraction, where software components are dominant, several optimization steps are demonstrated, including DSP code optimization and test generation. Throughout the book, EAs are tested on real-world applications and on large problem instances. For each application the main criteria for the successful application in the corresponding domain are discussed. In addition, contributions from leading international researchers provide the reader with a variety of perspectives, including a special focus on the combination of EAs with problem specific heuristics. Evolutionary Algorithms for Embedded System Design is an excellent reference for both practitioners working in the area of circuit and system design and for researchers in the field of evolutionary concepts.

SISDEP 95 provides an international forum for the presentation of state-of-the-art research and development results in the area of numerical process and device simulation. Continuously shrinking device dimensions, the use of new materials, and advanced processing steps in the manufacturing of semiconductor devices require new and improved software. The trend towards increasing complexity in structures and process technology demands advanced models describing all basic effects and sophisticated two and three dimensional tools for almost arbitrarily designed geometries. The book contains the latest results obtained by scientists from more than 20 countries on process simulation and modeling, simulation of process equipment, device modeling and simulation of novel devices, power semiconductors, and sensors, on device simulation and parameter extraction for circuit models, practical application of simulation, numerical methods, and software."

Cell-based design methodologies have dominated layout generation of digital circuits. Unfortunately, the growing demands for transparent process portability, increased performance, and low-level device sizing for timing/power are poorly handled in a fixed cell library. Direct Transistor-Level Layout For Digital Blocks proposes a direct transistor-level layout approach for small blocks of custom digital logic as an alternative that better accommodates demands for device-level flexibility. This approach captures essential shape-level optimizations, yet scales easily to netlists with thousands of devices, and incorporates timing optimization during layout. The key idea is early identification of essential diffusion-merged MOS device groups, and their preservation in an uncommitted geometric form until the very end of detailed placement. Roughly speaking, essential groups are extracted early from the transistor-level netlist, placed globally, optimized locally, and then finally committed each to a specific shape-level form while concurrently optimizing for both density and routability. The essential flaw in prior efforts is an over-reliance on geometric assumptions from large-scale cell-based layout algorithms. Individual transistors may seem simple, but they do not pack as gates do. Algorithms that ignore these shape-level issues suffer the consequences when thousands of devices are poorly packed. The approach described in this book can pack devices much more densely than a typical cell-based layout. Direct Transistor-Level Layout For Digital Blocks is a comprehensive reference work on device-level layout optimization, which will be valuable to CAD tool and circuit designers.

Application-Driven Architecture Synthesis describes the state of the art of architectural synthesis for complex real-time processing. In order to deal with the stringent timing requirements and the intricacies of complex real-time signal and data processing, target architecture styles and target application domains have been adopted to make the synthesis approach feasible. These approaches are also heavily application-driven, which is illustrated by many realistic demonstrations, used as examples in the book. The focus is on domains where application-specific solutions are attractive, such as significant parts of audio, telecom, instrumentation, speech, robotics, medical and automotive processing, image and video processing, TV, multi-media, radar, sonar. Application-Driven Architecture Synthesis is of interest to both academics and senior design engineers and CAD managers in industry. It provides an excellent overview of what capabilities to expect from future practical design tools, and includes an extensive bibliography.

Testing techniques for VLSI circuits are undergoing many exciting changes. The predominant method for testing digital circuits consists of applying a set of input stimuli to the IC and monitoring the logic levels at primary outputs. If, for one or more inputs, there is a discrepancy between the observed output and the expected output then the IC is declared to be defective. A new approach to testing digital circuits, which has come to be known as IDDQ testing, has been actively researched for the last fifteen years. In IDDQ testing, the steady state supply current, rather than the logic levels at the primary outputs, is monitored. Years of research suggests that IDDQ testing can significantly improve the quality and reliability of fabricated circuits. This has prompted many semiconductor manufacturers to adopt this testing technique, among them Philips Semiconductors, Ford Microelectronics, Intel, Texas Instruments, LSI Logic, Hewlett-Packard, SUN microsystems, Alcatel, and SGS Thomson. This increase in the use of IDDQ testing should be of interest to three groups of individuals associated with the IC business: Product Managers and Test Engineers, CAD Tool Vendors and Circuit Designers. Introduction to IDDQ Testing is designed to educate this community. The authors have summarized in one volume the main findings of more than fifteen years of research in this area.

The combination of VLSI process technology and real-time digital signal processing (DSP) has brought a break-through in information technology. This rapid technical (r)evolution allows the integration of ever more complex systems on a single chip. However, these technology and integration advances have not been matched by an increase in design productivity, causing technology to leapfrog the design of integrated circuits (ICs). The success of these emerging 'systems-on-a-chip' (SOC) can only be guaranteed by a systematic and formal design methodology, possibly automated in computer-aided design (CAD) tools, and effective re-use of existing intellectual property (IP). In this book, a contribution is made to the modeling, timing verification and analysis, and the automatic synthesis of integrated real-time DSP systems. Existing literature in these three domains is extensively reviewed, making this book the first to give a comprehensive overview of existing techniques.The emphasis throughout the book is on the support and guaranteeing of the real-time aspect and constraints of these systems, which avoids time consuming design iterations and safeguards the ever shrinking time-to-market. The proposed 'Multi-Thread Graph' (MTG) system model features two-layers, unifying a (timed) Petri net and a control-data flow graph. Its unique interface between both models offers the best of two worlds and introduces an extra abstraction level hiding the operation-level details which are unnecessary during global system exploration. The formulated timing analysis and verification approach supports the calculation of temporal separation between different MTG entities as well as realistic performance metrics for highly concurrent systems. The synthesis methodology focuses on managing the task-level concurrency (i.e. task scheduling), as part of a proposed overall system design meta flow. It emphasizes performance and timing aspects ('timeliness'), while minimizing processor cost overhead as driven by high-level cost estimators.The approach is new in the abstraction level it employs, and in its optimal hybrid dynamic/static scheduling policy which, driven by cost estimators, selects the scheduling policy for each behavior. At the low-level, RTOS synthesis generates an application-specific scheduler for the software component. The proposed synthesis methodology (at the task-level) is asserted to yield most optimal results when employed before the hardware/software partition is made. At this level, the distinction between these two is minimal, such that all steps in the design trajectory can be shared, thereby reducing the system cost significantly and allowing tighter satisfaction of timing/performance constraints. From the Foreword: This book is the first comprehensive treatment of software, and more general, system, generation (synthesis) techniques based on formal models. It can be used as a very valuable reference to understand the development of the field of embedded software design, and of system design and synthesis in general. The book offers an invaluable help to researchers and practitioners of the field of embedded system design. Prof. Alberto Sangiovanni-Vincentelli, Edgar L. and Harold H.Buttner Professor of Electrical Engineering and Computer Science, University of California, Berkeley, Chief Technology Advisor, Cadence Design Systems.

One of the main applications of VHDL is the synthesis of electronic circuits. Circuit Synthesis with VHDL is an introduction to the use of VHDL logic (RTL) synthesis tools in circuit design. The modeling styles proposed are independent of specific market tools and focus on constructs widely recognized as synthesizable by synthesis tools. A statement of the prerequisites for synthesis is followed by a short introduction to the VHDL concepts used in synthesis. Circuit Synthesis with VHDL presents two possible approaches to synthesis: the first starts with VHDL features and derives hardware counterparts; the second starts from a given hardware component and derives several description styles. The book also describes how to introduce the synthesis design cycle into existing design methodologies and the standard synthesis environment. Circuit Synthesis with VHDL concludes with a case study providing a realistic example of the design flow from behavioral description down to the synthesized level. Circuit Synthesis with VHDL is essential reading for all students, researchers, design engineers and managers working with VHDL in a synthesis environment.

For many years, the dominant fault model in automatic test pattern gen eration (ATPG) for digital integrated circuits has been the stuck-at fault model. The static nature of stuck-at fault testing when compared to the extremely dynamic nature of integrated circuit (IC) technology has caused many to question whether or not stuck-at fault based testing is still viable. Attempts at answering this question have not been wholly satisfying due to a lack of true quantification, statistical significance, and/or high computational expense. In this monograph we introduce a methodology to address the ques tion in a manner which circumvents the drawbacks of previous approaches. The method is based on symbolic Boolean functional analyses using Or dered Binary Decision Diagrams (OBDDs). OBDDs have been conjectured to be an attractive representation form for Boolean functions, although cases ex ist for which their complexity is guaranteed to grow exponentially with input cardinality. Classes of Boolean functions which exploit the efficiencies inherent in OBDDs to a very great extent are examined in Chapter 7. Exact equa tions giving their OBDD sizes are derived, whereas until very recently only size bounds have been available. These size equations suggest that straight forward applications of OBDDs to design and test related problems may not prove as fruitful as was once thought."

This volume is about automation - automation in design, automation in manufacturing, and automation in production. Automation is essen tial for increased productivity of quality products at reduced costs. That even partial or piecemeal automation of a production facility can deliver dramatic improvements in productivity has been amply demon strated in many a real-life situation. Hence, currently, great ef forts are being devoted to research and development of general as well special methodologies of and tools for automation. This volume re ports on some of these methodologies and tools. In general terms, methodologies for automation can be divided into two groups. There are situations where a process, whether open-loop or closed-loop, is fairly clearly understood. In such a situation, it is possible to create a mathematical model and to prescribe a mathe matical procedure to optimize the output. If such mathematical models and procedures are computationally tractable, we call the correspond ing automation - algorithmic or parametric programming. There is, however, a second set of situations which include process es that are not well understood and the available mathematical models are only approximate and discrete. While there are others for which mathematical procedures are so complex and disjoint that they are computationally intractable. These are the situations for which heuristics are quite suitable for automation. We choose to call such automation, knowledge-based automation or heuristic programming."

In the design of any visual objects, the work becomes much easier if previous designs are utilized. Computer graphics is becoming increasingly important simply because it greatly helps in utilizing such previous designs. Here, "previous designs" signifies both design results and design procedures. The objects designed are diverse. For engineers, these objects could be machines or electronic circuits, as discussed in Chap. 3, ''CA~/CAM. '' Physicians often design models of a patient's organs from computed tomography images prior to surgery or to assist in diagnosis. This is the subject of Chap. 8, "Medical Graphics. " Chapter 7, "Computer Art," deals with the way in which artists use computer graphics in creating beautiful visual images. In Chap. 1, "Computational Geometry," a firm basis is provided for the definition of shapes in designed objects; this is a typical technical area in which computer graphics is constantly making worldwide progress. Thus, the present volume, reflecting international advances in these and other areas of computer graphics, provides every potential or actual graphics user with the essential up-to-date information. There are, typically, two ways of gathering this current information. One way is to invite international authorities to write on their areas of specialization. Usually this works very well if the areas are sufficiently established that it is possible to judge exactly who knows what. Since computer graphics, however, is still in its developmental stage, this method cannot be applied.

* Provides simple, conceptual descriptions of everyday technologies * Includes clear examples and diagrams that demonstrate the principles and techniques, not just a "how-to" punch list * Covers advanced topics for readers who want to dive into the deep end of the technology pool * Avoids jargon-where terminology does appear, the text will provide clear, concise definitions

This book constitutes the refereed proceedings of the European Design Science Symposium, EDSS 2011, held in Leixlip, Ireland, in October 2011 held in conjunction with the Intel European Research and Innovation Conference, ERIC 2011. The 15 revised full papers presented were carefully reviewed and selected from various submissions. The papers are organized in topical sections on design science and processes; evaluation and utility; and applying design science.

It is now a decade since the appearance of W. Diffie and M. E. Hellmann's startling paper, "New Directions in Cryptography." This paper not only established the new field of public-key cryptography but also awakened scientific interest in secret-key cryptography, a field that had been the almost exclusive domain of secret agencies and mathematical hobbyist. A number of ex cellent books on the science of cryptography have appeared since 1976. In the main, these books thoroughly treat both public-key systems and block ciphers (i. e. secret-key ciphers with no memo ry in the enciphering transformation) but give short shrift to stream ciphers (i. e., secret-key ciphers wi th memory in the enciphering transformation). Yet, stream ciphers, such as those . implemented by rotor machines, have played a dominant role in past cryptographic practice, and, as far as I can determine, re main still the workhorses of commercial, military and diplomatic secrecy systems. My own research interest in stream ciphers found a natural re sonance in one of my doctoral students at the Swiss Federal Institute of Technology in Zurich, Rainer A. Rueppe1. As Rainer was completing his dissertation in late 1984, the question arose as to where he should publish the many new results on stream ciphers that had sprung from his research."

This book constitutes the refereed proceedings of the 9th International Conference on Cooperative Design, Visualization, and Engineering, CDVE 2012, held in Osaka, Japan, in September 2012. The 36 revised full papers presented were carefully reviewed and selected from numerous submissions. The papers cover the topics of cooperative engineering, basic theories, methods and technologies that support CDVE, cooperative design, visualization and applications.

ThIS IS an English verSIOn of the book m two volumes, entitled "KeiJo Shon Kogaku (1), (2)" (Nikkan Kogyo Shinbun Co.) written in Japanese. The purpose of the book is a umfied and systematic exposition of the wealth of research results m the field of mathematical representation of curves and surfaces for computer aided geometric design that have appeared in the last thirty years. The material for the book started hfe as a set of notes for computer aided geometnc design courses which I had at the graduate schools of both computer SCIence, the umversity of Utah m U.S.A. and Kyushu Institute of Design in Japan. The book has been used extensively as a standard text book of curves and surfaces for students, practtcal engmeers and researchers. With the aim of systematic expositIOn, the author has arranged the book in 8 chapters: Chapter 0: The sIgmficance of mathemattcal representations of curves and surfaces is explained and histoncal research developments in this field are revIewed. Chapter 1: BasIc mathematical theones of curves and surfaces are reviewed and summanzed. Chapter 2: A classical mterpolation method, the Lagrange interpolation, is discussed. Although its use is uncommon in practice, this chapter is helpful in understanding Chaps. 4 and 6. Chapter 3: This chapter dIscusses the Coons surface in detail, which is one of the most important contributions in this field. Chapter 4: The fundamentals of spline functions, spline curves and surfaces are discussed in some detail.

The total integration of the process of designing, manufacturing, and supporting a product from the earliest conceptual phase to the time it is removed from service remains an unfulfilled dream. Yet, when we look at the enormity of the process of integration even for the most simply conceived and manufactured items, we can recognize that substantial progress has been and is being made. It is our nature to be dissatisfied with near term progress, but when we realize how short a time the tools to do that integration have been available, the progress is clearly noteworthy - considering the multitudes of subjects we have to deal with. Most of the integration problems we confront today are multidisciplinary in nature. They require not only the knowledge and experience in a variety of fields but also good cooperation from different disciplined organizations to adequately comprehend and solve such problems. In Volume I we have many examples that reflect the current state of the art in integration of engineer ing and production processes. The papers for Volume I have been arranged in a more or less logical order of conceptual. design, computer-based modeling, analysis, production, and manufacturing. Chapter I is devoted to those with a design and geometrie modeling emphasis; Chapter II is devoted to an engineering analysis emphasis; and Chapter III to a production/manufacturing emphasis."

Are memory applications more critical than they have been in the past? Yes, but even more critical is the number of designs and the sheer number of bits on each design. It is assured that catastrophes, which were avoided in the past because memories were small, will easily occur if the design and test engineers do not do their jobs very carefully. High Performance Memory Testing: Design Principles, Fault Modeling and Self Test is based on the author's 20 years of experience in memory design, memory reliability development and memory self test. High Performance Memory Testing: Design Principles, Fault Modeling and Self Test is written for the professional and the researcher to help them understand the memories that are being tested.

Digital Systems Design and Prototyping: Using Field Programmable Logic and Hardware Description Languages, Second Edition covers the subject of digital systems design using two important technologies: Field Programmable Logic Devices (FPLDs) and Hardware Description Languages (HDLs). These two technologies are combined to aid in the design, prototyping, and implementation of a whole range of digital systems from very simple ones replacing traditional glue logic to very complex ones customized as the applications require. Three HDLs are presented: VHDL and Verilog, the widely used standard languages, and the proprietary Altera HDL (AHDL). The chapters on these languages serve as tutorials and comparisons are made that show the strengths and weaknesses of each language. A large number of examples are used in the description of each language providing insight for the design and implementation of FPLDs. With the addition of the Altera UP-1 prototyping board, all examples can be tested and verified in a real FPLD. Digital Systems Design and Prototyping: Using Field Programmable Logic and Hardware Description Languages, Second Edition is designed as an advanced level textbook as well as a reference for the professional engineer.

The role of arithmetic in datapath design in VLSI design has been increasing in importance over the last several years due to the demand for processors that are smaller, faster, and dissipate less power. Unfortunately, this means that many of these datapaths will be complex both algorithmically and circuit wise. As the complexity of the chips increases, less importance will be placed on understanding how a particular arithmetic datapath design is implemented and more importance will be given to when a product will be placed on the market. This is because many tools that are available today, are automated to help the digital system designer maximize their efficiently. Unfortunately, this may lead to problems when implementing particular datapaths. The design of high-performance architectures is becoming more compli cated because the level of integration that is capable for many of these chips is in the billions. Many engineers rely heavily on software tools to optimize their work, therefore, as designs are getting more complex less understanding is going into a particular implementation because it can be generated automati cally. Although software tools are a highly valuable asset to designer, the value of these tools does not diminish the importance of understanding datapath ele ments. Therefore, a digital system designer should be aware of how algorithms can be implemented for datapath elements. Unfortunately, due to the complex ity of some of these algorithms, it is sometimes difficult to understand how a particular algorithm is implemented without seeing the actual code."

The craft of designing mathematical models of dynamic objects offers a large number of methods to solve subproblems in the design, typically parameter estimation, order determination, validation, model reduc tion, analysis of identifiability, sensi tivi ty and accuracy. There is also a substantial amount of process identification software available. A typi cal 'identification package' consists of program modules that implement selections of solution methods, coordinated by supervising programs, communication, and presentation handling file administration, operator of results. It is to be run 'interactively', typically on a designer's 'work station' . However, it is generally not obvious how to do that. Using interactive identification packages necessarily leaves to the user to decide on quite a number of specifications, including which model structure to use, which subproblems to be solved in each particular case, and in what or der. The designer is faced with the task of setting up cases on the work station, based on apriori knowledge about the actual physical object, the experiment conditions, and the purpose of the identification. In doing so, he/she will have to cope with two basic difficulties: 1) The com puter will be unable to solve most of the tentative identification cases, so the latter will first have to be form11lated in a way the computer can handle, and, worse, 2) even in cases where the computer can actually produce a model, the latter will not necessarily be valid for the intended purpose."